公开(公告)号：US06218723B1

公开(公告)日：2001-04-17

申请号：US09390862

申请日：1999-09-03

申请人： Philippe Delpech ,  Etienne Robilliart ,  Didier Dutartre

发明人： Philippe Delpech ,  Etienne Robilliart ,  Didier Dutartre

IPC分类号： H01L2943

CPC分类号： H01L28/40

摘要： A capacitor integrated on a silicon substrate includes a first electrode made of highly doped polysilicon, a thin silicon oxide layer, a second electrode made of polysilicon and a silicide layer covering the second electrode. The second electrode has a high dopant concentration at its interface with the silicon oxide layer and a low or medium dopant concentration at its interface with the silicide layer.

摘要翻译： 集成在硅衬底上的电容器包括由高掺杂多晶硅制成的第一电极，薄氧化硅层，由多晶硅制成的第二电极和覆盖第二电极的硅化物层。 第二电极在其与氧化硅层的界面处具有高掺杂剂浓度，并且在其与硅化物层的界面处具有低或中等掺杂剂浓度。

公开(公告)号：US6132806A

公开(公告)日：2000-10-17

申请号：US106571

申请日：1998-06-29

申请人： Didier Dutartre

发明人： Didier Dutartre

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  C23C16/24

CPC分类号： H01L29/4966 ,  H01L21/2807

摘要： The present invention relates to a method of formation of an Si.sub.1-x Ge.sub.x MOS transistor gate where x is higher than 50%, on an silicon oxide gate insulator layer, consisting of depositing an Si.sub.1-y Ge.sub.y layer of thickness lower than 10 nm, where 0 50%. The desired thickness ranges, for example, between 20 nm and 200 nm. x and z range, for example, between 80% and 90%.

摘要翻译： 本发明涉及一种在氧化硅栅极绝缘体层上形成x高于50％的Si1-xGex MOS晶体管栅极的方法，该方法包括沉积厚度低于10nm的Si1-yGey层，其中0 50％。 期望的厚度范围例如在20nm和200nm之间。 x和z范围，例如在80％和90％之间。

公开(公告)号：US5252181A

公开(公告)日：1993-10-12

申请号：US808745

申请日：1991-12-17

申请人： Didier Dutartre ,  Daniel Bensahel ,  Jorge L. Regolini

发明人： Didier Dutartre ,  Daniel Bensahel ,  Jorge L. Regolini

IPC分类号： B08B7/00 ,  C23C14/02 ,  C23F4/00 ,  C23G5/00 ,  H01L21/306 ,  B44C1/22

CPC分类号： H01L21/02046 ,  B08B7/0035 ,  C23C14/022 ,  C23F4/00

摘要： Method for cleaning, with plasma, the surface of a substrate before another treatment, consisting:in a first cleaning step, in negatively polarizing the substrate and in subjecting it to an argon plasma, andin a second cleaning step, in subjecting the pretreated substrate to a hydrogen plasma, in order to ensure an efficient cleaning of the surface of the substrate.Application to the prior cleaning of a silicon substrate intended to receive an epitaxy.

摘要翻译： 用于在另一处理之前用等离子体清洗基板的表面的方法包括：在第一清洁步骤中，使基板负极化并使其经受氩等离子体，并且在第二清洁步骤中，对经预处理的基板 到氢等离子体，以确保有效地清洁基底的表面。 适用于预先清洁旨在接收外延的硅衬底。

公开(公告)号：US07776679B2

公开(公告)日：2010-08-17

申请号：US12175877

申请日：2008-07-18

申请人： Nicolas Loubet ,  Didier Dutartre ,  Frederic Boeuf

发明人： Nicolas Loubet ,  Didier Dutartre ,  Frederic Boeuf

IPC分类号： H01L21/8238

CPC分类号： H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639

摘要： A method for manufacturing silicon wells of various crystallographic orientations in a silicon support, including the steps of: forming a silicon layer having a first orientation on a silicon substrate having a second orientation; forming insulating walls, defining wells extend at least down to the border between the silicon substrate and the silicon layer; performing, in first wells, a chemical vapor etch (CVE) of the silicon layer by means of hydrochloric acid, in an epitaxy reactor, at a temperature ranging between 700° C. and 950° C.; and performing, in the first wells, a vapor-phase epitaxy on the silicon substrate in the presence of a precursor of silicon and hydrochloric acid, at a temperature ranging between 700° C. and 900° C. and up to the upper surface of the silicon layer.

摘要翻译： 一种用于制造硅载体中各种晶体取向硅阱的方法，包括以下步骤：在具有第二取向的硅衬底上形成具有第一取向的硅层; 形成绝缘壁，限定阱至少向下延伸到硅衬底和硅层之间的边界; 在外延反应器中，在700℃至950℃的温度范围内，通过盐酸在第一个阱中进行硅层的化学气相蚀刻（CVE）。 并且在第一个阱中，在硅和盐酸的前体存在下，在700℃和900℃之间的温度下，在硅衬底上进行气相外延，直到 硅层。

公开(公告)号：US06656812B1

公开(公告)日：2003-12-02

申请号：US09717825

申请日：2000-11-21

申请人： Michel Marty ,  Didier Dutartre ,  Alain Chantre ,  Sébastien Jouan ,  Pierre Llinares

发明人： Michel Marty ,  Didier Dutartre ,  Alain Chantre ,  Sébastien Jouan ,  Pierre Llinares

IPC分类号： H01L21331

CPC分类号： H01L29/0895

摘要： A vertical bipolar transistor includes a semiconductor substrate, an extrinsic collector layer in the semiconductor substrate, an intrinsic collector on the extrinsic collector, a lateral isolating region surrounding an upper part of the intrinsic collector, an offset extrinsic collector well, a base including a semiconductor region above the intrinsic collector and above the lateral isolating region including at least one silicon layer, and a doped emitter surrounded by the base. The doped emitter may include first and second parts. The first part may be formed from single-crystal silicon and in direct contact with the upper surface of the semiconductor region in a predetermined window in the upper surface above the intrinsic collector. The second part may be formed from polycrystalline silicon. The two parts of the emitter may be separated by a separating oxide layer spaced apart from the emitter-base junction of the transistor.

摘要翻译： 垂直双极晶体管包括半导体衬底，半导体衬底中的非本征集电极层，非本征集电极上的本征集电极，围绕本征集电极的上部的横向隔离区，偏移的外在集电极阱，包括半导体 在包含至少一个硅层的横向隔离区域上方以及由该基极包围的掺杂发射极之上。 掺杂发射器可以包括第一和第二部分。 第一部分可以由单晶硅形成，并且在本征收集器上方的上表面中的预定窗口中与半导体区域的上表面直接接触。 第二部分可以由多晶硅形成。 发射极的两个部分可以通过与晶体管的发射极 - 基极结间隔开的分离氧化物层来分离。

公开(公告)号：US06583451B2

公开(公告)日：2003-06-24

申请号：US09738870

申请日：2000-12-15

申请人： Thomas Skotnicki ,  Malgorzata Jurczak ,  Didier Dutartre

发明人： Thomas Skotnicki ,  Malgorzata Jurczak ,  Didier Dutartre

IPC分类号： H01L3300

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/76262 ,  H01L29/0673 ,  H01L29/0676

摘要： The process for fabricating a network of nanometric lines made of single-crystal silicon on an isolating substrate includes the production of a substrate comprising a silicon body having a lateral isolation defining a central part in the body. A recess is formed in the central part having a bottom wall made of dielectric material, a first pair of opposed parallel sidewalls made of dielectric material, and a second pair of opposed parallel sidewalls. At least one of the opposed parallel sidewalls of the second pair being formed from single-crystal silicon. The method further includes the epitaxial growth in the recess, from the sidewall made of single-crystal silicon of the recess, of an alternating network of parallel lines made of single-crystal SiGe alloy and of single-crystal silicon. Also, the lines made of single-crystal SiGe alloy are etched to form in the recess a network of parallel lines made of single-crystal silicon insulated from each other.

摘要翻译： 用于在隔离衬底上制造由单晶硅制成的纳米线网络的工艺包括制备包含限定主体中心部分的侧向隔离的硅体的衬底。 在具有由电介质材料制成的底壁的中心部分形成凹部，由电介质材料制成的第一对相对的平行侧壁和第二对相对的平行侧壁。 第二对的相对的平行侧壁中的至少一个由单晶硅形成。 该方法还包括从由凹槽的单晶硅制成的侧壁，由单晶SiGe合金和单晶硅制成的平行线的交替网络的凹槽中的外延生长。 此外，由单晶SiGe合金制成的线被蚀刻以在凹槽中形成由彼此绝缘的单晶硅硅制成的平行线的网络。

公开(公告)号：US4813781A

公开(公告)日：1989-03-21

申请号：US89556

申请日：1987-08-26

申请人： Annie Tissier ,  Didier Dutartre

发明人： Annie Tissier ,  Didier Dutartre

IPC分类号： G01B11/16 ,  G01N3/00 ,  H01L21/3105 ,  G01B9/02

CPC分类号： G01B11/165 ,  H01L21/3105 ,  G01N2203/0071

摘要： In a method for measuring the flowing of the material, the following steps: forming an array of parallel strips of said material constituting a diffraction grating; submitting said grating at the same conditions as the material, the flowing of which is to be monitored; illuminating the grating by a single wavelength light beam and observing the diffracted light.

摘要翻译： 在用于测量材料流动的方法中，以下步骤：形成构成衍射光栅的所述材料的平行条带阵列; 在与材料相同的条件下提交所述光栅，其流动被监视; 通过单个波长光束照射光栅并观察衍射光。

公开(公告)号：US4678538A

公开(公告)日：1987-07-07

申请号：US853906

申请日：1986-04-21

申请人： Michel Haond ,  Daniel Bensahel ,  Didier Dutartre

发明人： Michel Haond ,  Daniel Bensahel ,  Didier Dutartre

IPC分类号： H01L21/20 ,  C30B13/34 ,  H01L21/306 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

CPC分类号： C30B13/34

摘要： Process for the production of an oriented monocrystalline silicon film with localized defects on an insulating support.This process consists of covering a monocrystalline silicon support of orientation (100) with a SiO.sub.2 layer, producing in the latter a configuration having in the form of oriented (100) parallel insulating strips, an alternation of overhanging parts and recessed parts carrying out the etching of the SiO.sub.2 layer in order to locally form at the ends of said layer at least one opening, said etching being continued until the substrate is exposed, depositing on the etched SiO.sub.2 layer a silicon film, covering the silicon film with an encapsulating layer, carrying out a heat treatment of the structure obtained in order to recrystallize the silicon film in monocrystalline form with the same orientation as the substrate and eliminating the encapsulating layer.

摘要翻译： 用于在绝缘支撑件上制造具有局部缺陷的取向单晶硅膜的方法。 该方法包括用SiO 2层覆盖取向（100）的单晶硅支撑体，后者产生具有取向（100）平行绝缘条形式的构型，突出部分的交替和进行蚀刻的凹陷部分 的SiO 2层，以在所述层的端部局部形成至少一个开口，所述蚀刻继续进行，直到基板被暴露，在蚀刻的SiO 2层上沉积硅膜，用封装层覆盖硅膜，承载 对获得的结构进行热处理，以便以与衬底相同的取向以单晶形式重结晶硅膜并消除封装层。

公开(公告)号：US08524522B2

公开(公告)日：2013-09-03

申请号：US12963792

申请日：2010-12-09

申请人： Michel Marty ,  Didier Dutartre ,  Francois Roy ,  Pascal Besson ,  Jens Prima

发明人： Michel Marty ,  Didier Dutartre ,  Francois Roy ,  Pascal Besson ,  Jens Prima

IPC分类号： H01L21/00 ,  H01L21/46 ,  H01L31/0232 ,  H01L27/148

CPC分类号： H01L27/14687 ,  H01L21/2007 ,  H01L21/30604 ,  H01L21/76256 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/1812

摘要： A process for producing a microelectronic device includes producing a first semiconductor substrate which includes a first layer and a second layer present between a first side and a second side of the substrate. First electronic components and an interconnecting part are produced on and above the second side. The substrate is then thinned by a first selective etch applied from the first side and stopping on the first layer followed by a second selective etch stopping on the second layer. A second substrate is attached over the interconnecting part. The electronic components may comprise optoelectronic devices which are illuminated through the second layer.

摘要翻译： 微电子器件的制造方法包括制造第一半导体衬底，该第一半导体衬底包括存在于衬底的第一侧和第二侧之间的第一层和第二层。 第一电子部件和互连部分在第二面上和上方产生。 然后通过从第一侧施加的第一选择性蚀刻将衬底减薄，并停止在第一层上，随后在第二层上进行第二选择性蚀刻停止。 第二衬底附接在互连部分上。 电子部件可以包括通过第二层照射的光电子器件。

公开(公告)号：US20090023275A1

公开(公告)日：2009-01-22

申请号：US12175877

申请日：2008-07-18

申请人： Nicolas Loubet ,  Didier Dutartre ,  Frederic Boeuf

发明人： Nicolas Loubet ,  Didier Dutartre ,  Frederic Boeuf

IPC分类号： H01L21/20

CPC分类号： H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639

摘要： A method for manufacturing silicon wells of various crystallographic orientations in a silicon support, including the steps of: forming a silicon layer having a first orientation on a silicon substrate having a second orientation; forming insulating walls, defining wells extend at least down to the border between the silicon substrate and the silicon layer; performing, in first wells, a chemical vapor etch (CVE) of the silicon layer by means of hydrochloric acid, in an epitaxy reactor, at a temperature ranging between 700° C. and 950° C.; and performing, in the first wells, a vapor-phase epitaxy on the silicon substrate in the presence of a precursor of silicon and hydrochloric acid, at a temperature ranging between 700° C. and 900° C. and up to the upper surface of the silicon layer.

摘要翻译： 一种用于制造硅载体中各种晶体取向硅阱的方法，包括以下步骤：在具有第二取向的硅衬底上形成具有第一取向的硅层; 形成绝缘壁，限定阱至少向下延伸到硅衬底和硅层之间的边界; 在外延反应器中，在700℃至950℃的温度范围内，通过盐酸在第一个阱中进行硅层的化学气相蚀刻（CVE）。 并且在第一个阱中，在硅和盐酸的前体存在下，在700℃和900℃之间的温度范围内，在硅衬底上进行气相外延，直到上述表面 硅层。