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201 条记录 (耗时 0.035 秒)

    Semiconductor device having a device isolation structure
    11.
    发明授权
    Semiconductor device having a device isolation structure 有权
    具有器件隔离结构的半导体器件

    公开(公告)号：US08368169B2

    公开(公告)日：2013-02-05

    申请号：US12897095

    申请日：2010-10-04

    申请人： Seunguk Han ,  Satoru Yamada ,  Young Jin Choi

    发明人： Seunguk Han ,  Satoru Yamada ,  Young Jin Choi

    IPC分类号： H01L21/70

    CPC分类号： H01L21/823481 ,  H01L21/76229 ,  H01L21/823425

    摘要： An example semiconductor device includes a trench formed in a semiconductor substrate to define an active region, a filling dielectric layer provided within the trench, an oxide layer provided between the filling dielectric layer and the trench, a nitride layer provided between the oxide layer and the filling dielectric layer, and a barrier layer provided between the oxide layer and the nitride layer.

    摘要翻译： 示例性半导体器件包括形成在半导体衬底中以限定有源区的沟槽，设置在沟槽内的填充介电层，设置在填充介电层和沟槽之间的氧化物层，设置在氧化物层和 填充介电层，以及设置在氧化物层和氮化物层之间的阻挡层。

    Coil component
    12.
    发明授权
    Coil component 有权
    线圈组件

    公开(公告)号：US08207808B2

    公开(公告)日：2012-06-26

    申请号：US13093299

    申请日：2011-04-25

    申请人： Satoru Yamada ,  Yoshiyuki Hatayama

    发明人： Satoru Yamada ,  Yoshiyuki Hatayama

    IPC分类号： H01F27/29

    CPC分类号： H01F27/29 ,  H01F17/04 ,  H01F27/292 ,  H01F41/10 ,  H01F2017/048 ,  Y10T29/49071 ,  Y10T29/49073

    摘要： A coil component includes a core formed by a magnetic material, a coil embedded in the core, a part of a terminal portion of the coil protruded from a side surface of the core, and a tabular terminal, a part thereof protruded from the side surface of the core and partly connected with the protruded part of the terminal portion of the coil. The protruded part of the terminal portion of the coil and the protruded part of the tabular terminal are respectively bent toward the bottom surface side of the core along the side surface of the core, and the protruded and bent part of the terminal portion of the coil is arranged between the protruded and bent part of the tabular terminal and the core.

    摘要翻译： 线圈部件包括由磁性材料形成的芯部，嵌入在芯部中的线圈，从芯部的侧表面突出的线圈的端子部分的一部分，以及从侧面突出的部分 并且部分地与线圈的端子部分的突出部分连接。 线圈的端子部分的突出部分和平板状端子的突出部分分别沿着芯的侧表面朝着芯的底表面侧弯曲，并且线圈的端子部分的突出和弯曲部分 布置在板状端子的突出部分和弯曲部分之间。

    Semiconductor device having silicon layer in a gate electrode
    13.
    发明申请
    Semiconductor device having silicon layer in a gate electrode 有权
    在栅电极中具有硅层的半导体器件

    公开(公告)号：US20090233433A1

    公开(公告)日：2009-09-17

    申请号：US12453737

    申请日：2009-05-20

    申请人： Satoru Yamada ,  Ryo Nagai

    发明人： Satoru Yamada ,  Ryo Nagai

    IPC分类号： H01L21/28

    CPC分类号： H01L21/28061 ,  H01L21/823842 ,  H01L29/4941

    摘要： A method for forming a semiconductor device includes, in order, consecutively depositing a gate insulating film and a silicon layer on a semiconductor substrate, implanting boron into the silicon layer, diffusing the boron by heat-treating the silicon layer, implanting phosphorous into the silicon layer, diffusing at least the phosphorous by heat-treating the silicon layer, and patterning the silicon layer by using a dry etching technique.

    摘要翻译： 一种形成半导体器件的方法依次包括在半导体衬底上沉积栅极绝缘膜和硅层，将硼注入到硅层中，通过热处理硅层来扩散硼，将磷注入到硅中 层，通过热处理硅层至少扩散至少磷，并通过使用干蚀刻技术图案化硅层。

    Semiconductor device including a fin field effect transistor and method of manufacturing the same
    14.
    发明申请
    Semiconductor device including a fin field effect transistor and method of manufacturing the same 有权
    包括鳍状场效应晶体管的半导体器件及其制造方法

    公开(公告)号：US20080099850A1

    公开(公告)日：2008-05-01

    申请号：US11976252

    申请日：2007-10-23

    申请人： Chang-Hoon Jeon ,  Satoru Yamada ,  Sang-Yeon Han ,  Jong-Man Park ,  Si-Ok Sohn

    发明人： Chang-Hoon Jeon ,  Satoru Yamada ,  Sang-Yeon Han ,  Jong-Man Park ,  Si-Ok Sohn

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7851 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

    摘要： In a fin field effect transistor (Fin FET)and a method of manufacturing the Fin FET, the Fin FET includes an active pattern inside which insulating layer patterns are formed, an isolation layer pattern enclosing a sidewall of the active pattern such that an opening exposing a sidewall of the active pattern located between the insulating layer patterns is formed, a gate electrode formed on the active pattern to fill the opening, impurity regions formed at portions of the active pattern adjacent to sidewalls of the gate electrode, an insulating interlayer covering the active pattern and the gate electrode and contact plugs formed through portions of the insulating interlayer and the active pattern adjacent to the sidewalls of the gate electrode such that the contact plug makes contact with the impurity region.

    摘要翻译： 在翅片场效应晶体管（Fin FET）和制造Fin FET的方法中，Fin FET包括其中形成绝缘层图案的有源图案，包围有源图案的侧壁的隔离层图案，使得开口露出 形成位于绝缘层图案之间的有源图案的侧壁，形成在有源图案上以填充开口的栅电极，形成在与栅电极的侧壁相邻的有源图案的部分处的杂质区，覆盖 有源图案和通过绝缘夹层的一部分和与栅电极的侧壁相邻的有源图案形成的栅电极和接触插塞，使得接触插塞与杂质区接触。

    Electrostatic chuck and substrate processing apparatus
    19.
    发明授权
    Electrostatic chuck and substrate processing apparatus 有权
    静电吸盘和基板处理装置

    公开(公告)号：US06785115B2

    公开(公告)日：2004-08-31

    申请号：US10057804

    申请日：2002-01-25

    申请人： Hideyoshi Tsuruta ,  Satoru Yamada ,  Kiyoshi Nashimoto ,  Naoki Miyazaki

    发明人： Hideyoshi Tsuruta ,  Satoru Yamada ,  Kiyoshi Nashimoto ,  Naoki Miyazaki

    IPC分类号： H02N2300

    CPC分类号： G03F7/707 ,  C23C16/4586 ,  G03F7/70708 ,  H01L21/6833 ,  Y10T279/23

    摘要： An electrostatic chuck is provided, having an insulation layer including a mount plane on which a wafer is mounted, an inner electrode provided in the insulation layer, and projecting portions protruding from the mount plane which include contact planes that contact the wafer. A backside gas flows into a space defined by the mount plane, the projecting portions, and the wafer under such a condition that the wafer is attracted to the mount plane so as to maintain the temperature uniformity of the wafer. The total areas of the contact planes of the projecting portions is not less than 5% and not more than 10% with respect to the area of the inner electrode, and the heights of the projecting portions are not less than 5 &mgr;m and not more than 10 &mgr;m.

    摘要翻译： 提供一种静电卡盘，其具有包括安装有晶片的安装平面的绝缘层，设置在绝缘层中的内部电极以及从安装面突出的突出部，该突出部包括与晶片接触的接触面。 背面气体在晶片被吸引到安装平面的条件下流入由安装平面，突出部分和晶片限定的空间中，以保持晶片的温度均匀性。 突出部的接触面的总面积相对于内部电极的面积为5％以上且10％以下，突出部的高度为5μm以上且不大于 10个妈妈

    Semiconductor integrated circuit device and process for manufacturing the same
    20.
    发明授权
    Semiconductor integrated circuit device and process for manufacturing the same 有权
    半导体集成电路器件及其制造方法

    公开(公告)号：US06770535B2

    公开(公告)日：2004-08-03

    申请号：US09767830

    申请日：2001-01-24

    申请人： Satoru Yamada ,  Kiyonori Oyu ,  Shinichiro Kimura

    发明人： Satoru Yamada ,  Kiyonori Oyu ,  Shinichiro Kimura

    IPC分类号： H01L21336

    CPC分类号： H01L27/10876 ,  H01L21/763 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894

    摘要： A reduction of the junction electric field intensity is accomplished in the semiconductor regions for the sources and drains of field effects transistors. For this purpose, a structure is provided where the gate electrodes 9 of the MIS.FETQs for memory cell selection of a DRAM are buried within the trenches 7a and 7b created in the semiconductor substrate 1. The bottom corners within the trench 7b are rounded so as to have a radius of curvature in accordance with the sub-threshold coefficient of the MIS.FETQs for memory cell selection. In addition, the gate insulating film 8 within the trench 7b is made to have a laminated structure of a thermal oxide film and a CVD film.

    摘要翻译： 在场效应晶体管的源极和漏极的半导体区域中实现结电场强度的降低。 为此，提供了一种结构，其中用于DRAM的存储单元选择的MIS.FETQ的栅电极9被埋在在半导体衬底1中形成的沟槽7a和7b内。沟槽7b内的底角被倒圆 具有根据用于存储器单元选择的MIS.FETQ的子阈值系数的曲率半径。 此外，使沟槽7b内的栅极绝缘膜8具有热氧化膜和CVD膜的层叠结构。