公开(公告)号：US07868662B2

公开(公告)日：2011-01-11

申请号：US12442649

申请日：2007-10-05

申请人： Norihide Kinugasa ,  Sachi Ota

发明人： Norihide Kinugasa ,  Sachi Ota

IPC分类号： H03K5/00

CPC分类号： H03K5/1252

摘要： There is provided a spike noise eliminating circuit that can eliminate reliably spike noise having a predetermined pulse width or smaller and transmit and output precisely a signal having a pulse width larger than the predetermined width. Spike noise in the input signal is eliminated by: detecting a coincidence in level of the input signal and a first delay signal obtained by delaying the input signal by a maximum pulse width of noise to be eliminated as a delay amount; and sampling the input signal or a second delay signal obtained by delaying the input signal by a certain period of time based on a signal obtained as a result of detecting the coincidence in level.

摘要翻译： 提供了一种尖峰噪声消除电路，其可以消除具有预定脉冲宽度或更小的可靠尖峰噪声，并且精确地发送和输出具有大于预定宽度的脉冲宽度的信号。 通过以下步骤来消除输入信号中的尖峰噪声：检测输入信号电平的一致性和通过将输入信号延迟最大待消除的噪声的脉冲宽度作为延迟量而获得的第一延迟信号; 并且基于作为检测到电平重合的结果获得的信号，对输入信号或通过将输入信号延迟一定时间段而获得的第二延迟信号进行采样。

公开(公告)号：US07046706B2

公开(公告)日：2006-05-16

申请号：US10719435

申请日：2003-11-21

申请人： Kenichi Tatehara ,  Haruhiko Mizuno ,  Norihide Kinugasa

发明人： Kenichi Tatehara ,  Haruhiko Mizuno ,  Norihide Kinugasa

IPC分类号： H01S3/00 ,  H01S3/30

CPC分类号： G11B7/126 ,  H01S5/042 ,  H01S5/0428

摘要： A laser diode driving device of the present invention can appropriately shorten the rising time and the falling time of a laser diode drive current in a range from a small current region to a large current region. In synchronization with the addition of an original input current from an input constant current source to the laser diode drive current amplifier, a differentiated current is added to the input current through a differentiation circuit and a pull-in type V-I conversion circuit, whereby the rising of a laser diode drive current is made abrupt. Furthermore, by increasing a gate potential of an input PchMOS transistor constituting the laser diode drive current amplifier by a differentiation circuit and a push-out type V-I conversion circuit in synchronization with the disconnection of an input current, the falling of a laser diode drive current is made abrupt.

摘要翻译： 本发明的激光二极管驱动装置可以在从小电流区域到大电流区域的范围内适当地缩短激光二极管驱动电流的上升时间和下降时间。 与从输入恒流源向激光二极管驱动电流放大器添加原始输入电流同步，微分电流通过微分电路和引入型VI转换电路加到输入电流上，由此上升 的激光二极管驱动电流突然。 此外，通过与输入电流的断开同步地通过微分电路和推出型VI转换电路来增加构成激光二极管驱动电流放大器的输入PchMOS晶体管的栅极电位，激光二极管驱动电流的下降 突然出现

公开(公告)号：US07113161B2

公开(公告)日：2006-09-26

申请号：US10704153

申请日：2003-11-10

申请人： Yoshio Nirasawa ,  Yuji Amano ,  Norihide Kinugasa

发明人： Yoshio Nirasawa ,  Yuji Amano ,  Norihide Kinugasa

IPC分类号： G09G3/36

CPC分类号： G09G5/18 ,  G09G3/20 ,  G09G3/3611 ,  G09G2310/0224

摘要： An influence of a switching noise caused by a horizontal shift clock to an oscillation frequency of a voltage controlled oscillator should be eliminated, to prevent an image shift in a PAL skip period. For this purpose, an odd number line horizontal shift clock from an odd number line horizontal shift clock generator and an even number line horizontal shift clock from an even number line horizontal shift clock generator are switched by a horizontal shift clock switching circuit, to be input to a color LCD panel. The horizontal shift clock switching circuit selects and outputs either the odd number line horizontal shift clock or the even number line horizontal shift clock according to a line identifying signal, in a normal period. By contrast, in a PAL skip period a selecting state of the shift clock is inverted immediately upon start of a PAL skip period, from a selecting state right before the start of the skip period, and the selecting state is again inverted in half a cycle of a horizontal scanning period.

摘要翻译： 应该消除由水平移位时钟引起的开关噪声对压控振荡器的振荡频率的影响，以防止PAL跳跃期间的图像偏移。 为此，来自奇数行水平移位时钟发生器的奇数行水平移位时钟和来自偶数行水平移位时钟发生器的偶数行水平移位时钟由水平移位时钟切换电路切换为输入 到彩色液晶面板。 在正常周期中，水平移位时钟切换电路根据线路识别信号选择并输出奇数行水平移位时钟或偶数行水平移位时钟。 相反，在PAL跳过时段中，从跳过时段开始之前的选择状态开始，跳闸时钟的选择状态立即反转，并且选择状态在半个周期内再次反转 的水平扫描期间。

公开(公告)号：US06921950B2

公开(公告)日：2005-07-26

申请号：US10294761

申请日：2002-11-15

申请人： Kenichi Tatehara ,  Norihide Kinugasa

发明人： Kenichi Tatehara ,  Norihide Kinugasa

IPC分类号： H01L21/822 ,  H01L21/8249 ,  H01L23/60 ,  H01L23/62 ,  H01L27/02 ,  H01L27/04 ,  H01L29/74 ,  H02H9/00 ,  H03K19/00 ,  H03K19/003

CPC分类号： H01L27/0266 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

摘要： In order to improve the robustness against electrostatic discharge, when power source terminal and ground terminal are open, of a semiconductor device having a first, a second and a third inverter that are connected in a cascade arrangement, the semiconductor device is provided not only with a first input protection circuit for guiding positive electrostatic discharges, that are applied from outside to a signal input terminal, to a power source line, and a second input protection circuit for guiding negative electrostatic discharges, that are applied from outside to the signal input terminal, to a ground line, but also an internal protection circuit for guiding electrostatic discharges that have been guided by the first input protection circuit to the power source line and flow from a P-channel MOS transistor in the second inverter towards the third inverter, to the ground line.

公开(公告)号：US20050156812A1

公开(公告)日：2005-07-21

申请号：US10995106

申请日：2004-11-24

申请人： Norihide Kinugasa ,  Yoshio Nirasawa ,  Hideo Hamaguchi ,  Sachi Ota

发明人： Norihide Kinugasa ,  Yoshio Nirasawa ,  Hideo Hamaguchi ,  Sachi Ota

IPC分类号： G06F3/14 ,  G09G3/36 ,  G09G5/00 ,  G09G5/14 ,  H04N5/66 ,  H04N5/93

CPC分类号： G09G5/008 ,  G06F3/1423 ,  G09G3/3611

摘要： A display panel control circuit includes a voltage controlled oscillator (VCO) for outputting a clock signal, a first-panel horizontal system pulse generation section, a second-panel horizontal system pulse generation section, a vertical system pulse generation section which is commonly used among the first and second panels, a phase comparator, and a smoothing element. The first-panel horizontal system pulse generation section and the second-panel horizontal system pulse generation section respectively generate a reference signal of a first-panel horizontal system output group and a reference signal of a second-panel horizontal system output group from signal VCOCLK1 output from the VCO. Thus, it is possible to simultaneously drive two different panels.

摘要翻译： 显示面板控制电路包括用于输出时钟信号的压控振荡器（VCO），第一面板水平系统脉冲产生部分，第二面板水平系统脉冲产生部分，垂直系统脉冲产生部分 第一和第二面板，相位比较器和平滑元件。 第一面板水平系统脉冲产生部分和第二面板水平系统脉冲产生部分分别从信号VCOCLK 1生成第一面板水平系统输出组的参考信号和第二面板水平系统输出组的参考信号 从VCO输出。 因此，可以同时驱动两个不同的面板。

公开(公告)号：US06825712B2

公开(公告)日：2004-11-30

申请号：US10385427

申请日：2003-03-12

申请人： Shiro Dosho ,  Takashi Morie ,  Hitoshi Kobayashi ,  Norihide Kinugasa ,  Masaomi Toyama

发明人： Shiro Dosho ,  Takashi Morie ,  Hitoshi Kobayashi ,  Norihide Kinugasa ,  Masaomi Toyama

IPC分类号： H03K500

CPC分类号： H03H11/04

摘要： In a front end that has a filter circuit and is used for a communication system having an asymmetric communication channel in which upstream and downstream data rates are different, a filter circuit for received signals, which is for filtering received signals, and a filter circuit for transmitted signals, which is for filtering transmitted signals, are provided. The filter circuit for received signals has an amplifier block including a plurality of amplifiers, a capacitor block including a plurality of capacitors and being connected to the plurality of amplifiers included in the amplifier block, and a first and a second resistor blocks each including a plurality of resistors. Either one of the first or the second resistor block is selectively switched so as to be connected to the amplifier block by a resistor block-switching circuit. The circuit scale is reduced since only one amplifier block and one capacitor block are commonly used for two kinds of filter circuits.

摘要翻译： 在具有滤波器电路的前端中，用于具有上行和下行数据速率不同的非对称通信信道的通信系统，用于对接收信号进行滤波的接收信号的滤波电路和用于 提供用于滤波发送信号的发送信号。 用于接收信号的滤波器电路具有包括多个放大器的放大器模块，包括多个电容器并且连接到放大器模块中所包括的多个放大器的电容器模块，以及包括多个放大器的第一和第二电阻块 的电阻。 选择性地切换第一或第二电阻器块中的任何一个，以便通过电阻器块切换电路连接到放大器块。 由于只有一个放大器块和一个电容器块通常用于两种滤波器电路，电路规模减小。

公开(公告)号：US5841389A

公开(公告)日：1998-11-24

申请号：US833965

申请日：1997-04-11

申请人： Norihide Kinugasa ,  Mitsuhiko Otani ,  Katsumi Hironaka ,  Shinichi Ogita

发明人： Norihide Kinugasa ,  Mitsuhiko Otani ,  Katsumi Hironaka ,  Shinichi Ogita

IPC分类号： H03M1/16 ,  H03M1/36

CPC分类号： H03M1/165 ,  H03M1/365

摘要： Provided is a two-step parallel A/D converter capable of operating at a higher speed than in the prior art and easily performing correction of upper bit data. An upper limit voltage V.sub.H of a voltage range for lower bit conversion is amplified on the basis of a median voltage V.sub.M of the voltage range by a second differential amplifier, and the amplified voltage is set to a high level reference voltage SUB.sub.H for lower bit conversion. A lower limit voltage V.sub.L of the voltage range is amplified on the basis of the median voltage V.sub.M by a third differential amplifier, and the amplified voltage is set to a low level reference voltage SUB.sub.L for lower bit conversion. A voltage V.sub.IN of an input analog signal is amplified on the basis of the voltage V.sub.M by a first differential amplifier, and lower bit data is obtained from a position between the voltage SUB.sub.H and the voltage SUB.sub.L which is occupied by an obtained voltage SUB.sub.IN. The voltages SUB.sub.H and SUB.sub.L are not changed by the voltage V.sub.IN of the input analog signal. Consequently, a settling time can be shortened more than in the prior art.

摘要翻译： 提供了一种两级并行A / D转换器，其能够以比现有技术更高的速度运行并且容易地执行高位数据的校正。 基于第二差分放大器的电压范围的中值电压VM来放大用于低位转换的电压范围的上限电压VH，并且将放大的电压设置为用于较低位转换的高电平参考电压SUBH 。 电压范围的下限电压VL由第三差分放大器基于中值电压VM放大，放大电压被设定为低电平基准电压SUBL用于低位转换。 输入模拟信号的电压VIN通过第一差分放大器基于电压VM放大，并且从电压SUBH和所获得的电压SUBIN占据的电压SUBL之间的位置获得低位数据。 电压SUBH和SUBL不会被输入模拟信号的电压VIN改变。 因此，与现有技术相比，可以缩短建立时间。

公开(公告)号：US20110285438A1

公开(公告)日：2011-11-24

申请号：US13114569

申请日：2011-05-24

申请人： Norihide Kinugasa ,  Koji Chiba

发明人： Norihide Kinugasa ,  Koji Chiba

IPC分类号： H03L7/06

CPC分类号： H03L7/087

摘要： A phase locked loop circuit comprises a charge pump fed with a phase error output signal; a loop filter charged or discharged with an output of the charge pump; an oscillator, an oscillating frequency of which is controlled by a voltage of the loop filter; and a frequency/phase comparator having a switching function which is fed with a reference signal and an output signal of the oscillator and outputs the phase error output signal; the frequency/phase comparator being configured to, based on a lock detection signal, switch between comparing frequencies by detecting rising edges of the reference signal and the comparison signal to detect a phase difference between the reference signal and the comparison signal, and comparing phases by detecting voltage levels of the reference signal and the comparison signal to detect a phase difference between the reference signal and the comparison signal.

摘要翻译： 锁相环电路包括馈送有相位误差输出信号的电荷泵; 用电荷泵的输出充电或放电的环路滤波器; 振荡器，其振荡频率由环路滤波器的电压控制; 以及具有开关功能的频率/相位比较器，该开关功能馈送有参考信号和振荡器的输出信号，并输出相位误差输出信号; 频率/相位比较器被配置为基于锁定检测信号，通过检测参考信号的上升沿和比较信号来比较频率之间的切换，以检测参考信号和比较信号之间的相位差，并且通过 检测参考信号和比较信号的电压电平，以检测参考信号和比较信号之间的相位差。

公开(公告)号：US20100246607A1

公开(公告)日：2010-09-30

申请号：US12750232

申请日：2010-03-30

申请人： Makoto KAWAJIRI ,  Norihide Kinugasa ,  Naohisa Hatani

发明人： Makoto KAWAJIRI ,  Norihide Kinugasa ,  Naohisa Hatani

IPC分类号： H04J3/00

CPC分类号： H04J3/047 ,  H04L7/0008

摘要： Each of n signal transition detection sections detects a transition of the signal level of at least one of a first input signal or a second input signal corresponding to the signal transition detection section. A time-division control section outputs a control pulse according to a system clock when a signal transition is detected by at least one of the n signal transition detection sections. Each of n output switching sections outputs either the first or the second input signal corresponding to the output switching section as a multiplexed signal according to the control pulse.

摘要翻译： n个信号转换检测部中的每一个检测与信号转变检测部对应的第一输入信号或第二输入信号中的至少一个的信号电平的转变。 当由n个信号转换检测部分中的至少一个检测到信号转换时，时分控制部分根据系统时钟输出控制脉冲。 n个输出切换部分中的每一个根据控制脉冲输出与输出切换部分相对应的第一或第二输入信号作为多路复用信号。

公开(公告)号：US07439936B2

公开(公告)日：2008-10-21

申请号：US10995106

申请日：2004-11-24

申请人： Norihide Kinugasa ,  Yoshio Nirasawa ,  Hideo Hamaguchi ,  Sachi Ota

发明人： Norihide Kinugasa ,  Yoshio Nirasawa ,  Hideo Hamaguchi ,  Sachi Ota

IPC分类号： G09G5/00

CPC分类号： G09G5/008 ,  G06F3/1423 ,  G09G3/3611

摘要： A display panel control circuit includes a voltage controlled oscillator (VCO) for outputting a clock signal, a first-panel horizontal system pulse generation section, a second-panel horizontal system pulse generation section, a vertical system pulse generation section which is commonly used among the first and second panels, a phase comparator, and a smoothing element. The first-panel horizontal system pulse generation section and the second-panel horizontal system pulse generation section respectively generate a reference signal of a first-panel horizontal system output group and a reference signal of a second-panel horizontal system output group from signal VCOCLK1 output from the VCO. Thus, it is possible to simultaneously drive two different panels.

摘要翻译： 显示面板控制电路包括用于输出时钟信号的压控振荡器（VCO），第一面板水平系统脉冲产生部分，第二面板水平系统脉冲产生部分，垂直系统脉冲产生部分 第一和第二面板，相位比较器和平滑元件。 第一面板水平系统脉冲产生部分和第二面板水平系统脉冲产生部分分别从信号VCOCLK 1生成第一面板水平系统输出组的参考信号和第二面板水平系统输出组的参考信号 从VCO输出。 因此，可以同时驱动两个不同的面板。