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133 条记录 (耗时 0.049 秒)

    Method of manufacturing semiconductor integrated circuit devices
    13.
    发明授权
    Method of manufacturing semiconductor integrated circuit devices 失效
    制造半导体集成电路器件的方法

    公开(公告)号：US07172853B2

    公开(公告)日：2007-02-06

    申请号：US10770413

    申请日：2004-02-04

    申请人： Norio Hasegawa ,  Akira Imai ,  Katsuya Hayano

    发明人： Norio Hasegawa ,  Akira Imai ,  Katsuya Hayano

    IPC分类号： G03F7/20 ,  G03C5/00

    CPC分类号： G03F7/70358 ,  G03F1/30 ,  G03F7/70283 ,  G03F7/70466

    摘要： To alleviate the absolute value control accuracy of phases in a mask having a groove shifter structure, transfer regions formed at different planar positions on the same plane of the same mask are subjected to a multiple exposure by scanning exposure. Although identical mask patterns are formed over the transfer regions respective groove shifters provided to these mask patterns are arranged opposite from each other.

    摘要翻译： 为了减轻具有凹槽移位结构的掩模中的相位的绝对值控制精度，形成在同一掩模的同一平面上的不同平面位置处的转印区域通过扫描曝光进行多次曝光。 虽然在传送区域上形成相同的掩模图案，但是设置在这些掩模图案上的相应凹槽移位器相互排列。

    Method of manufacturing semiconductor integrated circuit device optical mask therefor, its manufacturing method, and mask blanks
    14.
    发明授权
    Method of manufacturing semiconductor integrated circuit device optical mask therefor, its manufacturing method, and mask blanks 有权
    半导体集成电路器件的光掩模及其制造方法和掩模毛坯的制造方法

    公开(公告)号：US07125651B2

    公开(公告)日：2006-10-24

    申请号：US10674381

    申请日：2003-10-01

    申请人： Norio Hasegawa ,  Tsuneo Terasawa ,  Toshihiko Tanaka

    发明人： Norio Hasegawa ,  Tsuneo Terasawa ,  Toshihiko Tanaka

    IPC分类号： G03C5/00 ,  G03F9/00

    CPC分类号： G03F1/56 ,  G03F1/44 ,  G03F1/62 ,  G03F7/70983

    摘要： In order to suppress or prevent the occurrence of foreign matter in the manufacture of a semiconductor integrated circuit device by the use of a photo mask constituted in such a manner that a resist film is made to function as a light screening film, inspection or exposure treatment is carried out, when the photo mask 1PA1 has been mounted on a predetermined apparatus such as, e.g., an inspection equipment or aligner, in the state in which a mounting portion 2 of the predetermined apparatus is contacted with that region of a major surface of a mask substrate 1a of the photo mask 1PA1 in which a light shielding pattern 1b and a mask pattern 1mr, each formed of a resist film, on the major surface of the mask substrate 1a do not exist.

    摘要翻译： 为了通过使用以使抗蚀剂膜作为遮光膜的方式构成的光掩模来抑制或防止在制造半导体集成电路器件时发生异物，检查或曝光处理 当在预定设备的安装部分2与主要区域的区域接触的状态下，当光掩模1PA1已经安装在诸如检查设备或对准器的预定设备上时， 在掩模基板1a的主表面上不存在其中由抗蚀剂膜形成的遮光图案1b和掩模图案1mr的光掩模1 PA1的掩模基板1a的表面。

    Semiconductor integrated circuit device and manufacturing method thereof
    16.
    发明授权
    Semiconductor integrated circuit device and manufacturing method thereof 有权
    半导体集成电路器件及其制造方法

    公开(公告)号：US07042038B2

    公开(公告)日：2006-05-09

    申请号：US10653889

    申请日：2003-09-04

    申请人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Isamu Asano ,  Norio Hasegawa ,  Keizo Kawakita

    发明人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Isamu Asano ,  Norio Hasegawa ,  Keizo Kawakita

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/10852 ,  H01L27/10817

    摘要： An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width. In addition, a bit line (BL) is provided overlying the memory-cell select MISFET (Qs) in a manner such that the bit line extends in the X direction on the principal surface of the semiconductor substrate (1) with the same width and opposes its neighboring bit line (BL) at a distance or pitch that is wider than said width.

    摘要翻译： 在其中形成有用于选择构成DRAM的存储单元的DRAM存储单元的金属绝缘体半导体场效应晶体管（MISFET）（Qs）的有源区域（L）被布置成具有岛状图案， 在半导体衬底（1）的一个主表面上沿X方向线性地延伸。 存储单元选择MISFET（Qs）具有在半导体衬底（1）的主表面上沿着Y方向延伸的绝缘栅电极（字线WL），沿着其长度保持相同的宽度， 栅电极被布置成以比所述宽度窄的预定距离或间距与与其相邻的另一个栅电极（7）（字线WL）相对。 此外，位线（BL）以这样的方式设置在存储单元选择MISFET（Qs）上，使得位线在半导体衬底（1）的主表面上沿X方向以相同的宽度延伸，并且 以比所述宽度更宽的距离或间距来对置其相邻位线（BL）。

    Method of manufacturing an electronic device and a semiconductor integrated circuit device
    20.
    发明授权
    Method of manufacturing an electronic device and a semiconductor integrated circuit device 失效
    制造电子装置和半导体集成电路装置的方法

    公开(公告)号：US06660438B2

    公开(公告)日：2003-12-09

    申请号：US09983172

    申请日：2001-10-23

    申请人： Toshihiko Tanaka ,  Norio Hasegawa

    发明人： Toshihiko Tanaka ,  Norio Hasegawa

    IPC分类号： G03F900

    CPC分类号： G03F7/70466 ,  G03F1/32 ,  G03F1/70 ,  G03F7/70125

    摘要： A method of manufacturing an electronic device, such as a high-speed semiconductor integrated circuit device, with improved dimensional accuracy in transferring fine patterns. Photolithography for gate patterns and wiring patterns is carried out by exposing a halftone phase-shift mask having shade areas made of resist with an oblique illumination system, and photolithography for contact hole patterns is carried out by using a photomask having a metal shade film with metal alignment wafer marks.

    摘要翻译： 一种制造诸如高速半导体集成电路器件的电子器件的方法，其具有改进的精细图案转印尺寸精度。栅极图案和布线图案的光刻通过曝光具有阴影区域的半色调相移掩模 通过使用具有带有金属取向晶片标记的金属遮光膜的光掩模来进行接触孔图案的光刻。