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    Negatively biased isolation structures for pixel devices
    11.
    发明授权
    Negatively biased isolation structures for pixel devices 有权

    公开(公告)号：US11502120B2

    公开(公告)日：2022-11-15

    申请号：US16721320

    申请日：2019-12-19

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Kazufumi Watanabe ,  Chih-Wei Hsiung ,  Vincent Venezia ,  Young Woo Jung ,  Geunsook Park ,  Lindsay Alexander Grant

    IPC: H01L27/146

    Abstract: Backside illuminated sensor pixel structure. In one embodiment, and image sensor includes a plurality of pixels arranged in rows and columns of a pixel array that are disposed in a semiconductor substrate. Individual photodiodes of the pixel array are configured to receive an incoming light through a backside of the semiconductor substrate. A front side of the semiconductor substrate is opposite from the backside. A plurality of transistors disposed proximate to the front side of the semiconductor substrate, are arranged in a row along an outer perimeter of the photodiodes of the respective pixel; and a plurality of isolation structures arranged to bracket the row of transistors along the outer perimeter of the photodiodes. A plurality of contacts electrically contacting the plurality of isolation structures, and the contacts are configured to voltage-bias the plurality of isolation structures.

    Trench Isolation for Image Sensors
    13.
    发明申请
    Trench Isolation for Image Sensors 审中-公开

    公开(公告)号：US20190115388A1

    公开(公告)日：2019-04-18

    申请号：US15786874

    申请日：2017-10-18

    Applicant: OmniVision Technologies, Inc.

    Inventor： Young Woo Jung ,  Lindsay Grant ,  Dyson Tai ,  Vincent Venezia ,  Wei Zheng

    IPC: H01L27/148 ,  H01L27/146

    Abstract: An image sensor includes a plurality of photodiodes disposed in a semiconductor material to convert image light into image charge. A floating diffusion is disposed proximate to the plurality of photodiodes to receive the image charge from the plurality of photodiodes. A plurality of transfer transistors is coupled to transfer the image charge from the plurality of photodiodes into the floating diffusion in response to a voltage applied to the gate terminal of the plurality of transfer transistors. A first trench isolation structure extends from a frontside of the semiconductor material into the semiconductor material and surrounds the plurality of photodiodes. A second trench isolation structure extends from a backside of the semiconductor material into the semiconductor material. The second trench isolation structure is disposed between individual photodiodes in the plurality of photodiodes.

    BSI CMOS image sensor with improved phase detecting pixel
    14.
    发明授权
    BSI CMOS image sensor with improved phase detecting pixel 有权
    BSI CMOS图像传感器具有改进的相位检测像素

    公开(公告)号：US09443899B1

    公开(公告)日：2016-09-13

    申请号：US14932472

    申请日：2015-11-04

    Applicant: OmniVision Technologies, Inc.

    Inventor： Chia-Ying Liu ,  Chin-Poh Pang ,  Chih-Wei Hsiung ,  Vincent Venezia

    IPC: H01L27/146 ,  H04N5/369

    CPC classification number: H01L27/14643 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14683 ,  H01L27/14685

    Abstract: An improved back side illuminated (BSI) complementary metal oxide semiconductor (CMOS) image sensor, and associated methods, improve phase detecting capability. The BSI CMOS image sensor has an array of pixels that include a phase detecting pixel (PDP), a composite grid formed of a buried color filter array and composite metal/oxide grid, and a photodiode implant corresponding to the PDP. A PDP mask is fabricated with a deep trench isolation (DTI) structure proximate the PDP and positioned to mask at least part of the photodiode implant such that the PDP mask is positioned between the composite grid and the photodiode implant.

    Abstract translation: 改进的背面照明（BSI）互补金属氧化物半导体（CMOS）图像传感器及相关方法，提高相位检测能力。 BSI CMOS图像传感器具有包括相位检测像素（PDP），由掩埋滤色器阵列和复合金属/氧化物栅格形成的复合栅格和对应于PDP的光电二极管注入的像素阵列。 制造具有靠近PDP的深沟槽隔离（DTI）结构的PDP掩模，并且定位成掩模至少部分光电二极管注入，使得PDP掩模位于复合栅格和光电二极管植入物之间。

    Lateral light shield in backside illuminated imaging sensors
    15.
    发明授权
    Lateral light shield in backside illuminated imaging sensors 有权
    背面照明成像传感器的侧面防护罩

    公开(公告)号：US09177982B2

    公开(公告)日：2015-11-03

    申请号：US14319807

    申请日：2014-06-30

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Duli Mao ,  Dyson H. Tai ,  Vincent Venezia ,  Yin Qian ,  Gang Chen ,  Howard E. Rhodes

    IPC: H01L27/146

    CPC classification number: H01L27/1462 ,  H01L27/14623 ,  H01L27/1464 ,  H01L27/14685

    Abstract: A backside illuminated image sensor includes a semiconductor layer and a trench disposed in the semiconductor layer. The semiconductor layer has a frontside surface and a backside surface. The semiconductor layer includes a light sensing element of a pixel array disposed in a sensor array region of the semiconductor layer. The pixel array is positioned to receive external incoming light through the backside surface of the semiconductor layer. The semiconductor layer also includes a light emitting element disposed in a periphery circuit region of the semiconductor layer external to the sensor array region. The trench is disposed in the semiconductor layer between the light sensing element and the light emitting element.

    Abstract translation: 背面照明图像传感器包括设置在半导体层中的半导体层和沟槽。 半导体层具有前表面和背面。 半导体层包括设置在半导体层的传感器阵列区域中的像素阵列的光感测元件。 像素阵列被定位成接收穿过半导体层的背面的外部入射光。 半导体层还包括设置在传感器阵列区域外部的半导体层的外围电路区域中的发光元件。 沟槽设置在光感测元件和发光元件之间的半导体层中。

    Process to eliminate lag in pixels having a plasma-doped pinning layer
    16.
    发明授权
    Process to eliminate lag in pixels having a plasma-doped pinning layer 有权
    消除具有等离子体掺杂钉扎层的像素滞后的过程

    公开(公告)号：US08921187B2

    公开(公告)日：2014-12-30

    申请号：US13777197

    申请日：2013-02-26

    Applicant: OmniVision Technologies, Inc.

    Inventor： Gang Chen ,  Duli Mao ,  Hsin-Chih Tai ,  Vincent Venezia ,  Yin Qian ,  Howard E. Rhodes

    IPC: H01L27/148 ,  H01L27/146

    CPC classification number: H01L27/14689 ,  H01L27/1461 ,  H01L27/1463 ,  H01L27/14643

    Abstract: Embodiments of a process including depositing a sacrificial layer on the surface of a substrate over a photosensitive region, over the top surface of a transfer gate, and over at least the sidewall of the transfer gate closest to the photosensitive region, the sacrificial layer having a selected thickness. A layer of photoresist is deposited over the sacrificial layer, which is patterned and etched to expose the surface of the substrate over the photosensitive region and at least part of the transfer gate top surface, leaving a sacrificial spacer on the sidewall of the transfer gate closest to the photosensitive region. The substrate is plasma doped to form a pinning layer between the photosensitive region and the surface of the substrate. The spacing between the pinning layer and the sidewall of the transfer gate substantially corresponds to a thickness of the sacrificial spacer. Other embodiments are disclosed and claimed.

    Abstract translation: 一种方法的实施方案包括在光敏区域上方的基底表面上沉积牺牲层，在转移栅极的顶表面上，以及至少最靠近光敏区域的转移栅极的侧壁，牺牲层具有 选择厚度。 在牺牲层上沉积一层光致抗蚀剂，其被图案化和蚀刻以在基片的表面上在感光区域和至少部分传输栅极顶表面上露出基底表面，在传输门的侧壁上留下牺牲隔离物 到感光区域。 衬底是等离子体掺杂的，以在光敏区域和衬底的表面之间形成钉扎层。 钉扎层和转移门的侧壁之间的间隔基本上对应于牺牲间隔物的厚度。 公开和要求保护其他实施例。

    NEGATIVELY CHARGED LAYER TO REDUCE IMAGE MEMORY EFFECT
    17.
    发明申请
    NEGATIVELY CHARGED LAYER TO REDUCE IMAGE MEMORY EFFECT 审中-公开
    有意义的电荷层减少图像记忆效应

    公开(公告)号：US20140327102A1

    公开(公告)日：2014-11-06

    申请号：US14331652

    申请日：2014-07-15

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Howard E. Rhodes ,  Dajiang Yang ,  Gang Chen ,  Duli Mao ,  Vincent Venezia

    IPC: H01L31/0224 ,  H01L31/103

    CPC classification number: H01L31/0224 ,  H01L27/14609 ,  H01L27/1462 ,  H01L27/14643 ,  H01L31/103

    Abstract: An image sensor pixel includes a photodiode region having a first polarity doping type disposed in a semiconductor layer. A pinning surface layer having a second polarity doping type is disposed over the photodiode region in the semiconductor layer. A first polarity charge layer is disposed proximate to the pinning surface layer over the photodiode region. A contact etch stop layer is disposed over the photodiode region proximate to the first polarity charge layer. The first polarity charge layer is disposed between the pinning surface layer and the contact etch stop layer such that first polarity charge layer cancels out charge having a second polarity that is induced in the contact etch stop layer. The first polarity charge layer is disposed between a first one of a plurality of passivation layers and a second one of the plurality of passivation layers disposed over the photodiode region.

    Abstract translation: 图像传感器像素包括设置在半导体层中的具有第一极性掺杂型的光电二极管区域。 具有第二极性掺杂型的钉扎表面层设置在半导体层中的光电二极管区域的上方。 第一极性电荷层设置在光电二极管区域附近的钉扎表面层附近。 接触蚀刻停止层设置在靠近第一极性电荷层的光电二极管区域的上方。 第一极性电荷层设置在钉扎表面层和接触蚀刻停止层之间，使得第一极性电荷层抵消在接触蚀刻停止层中感应的具有第二极性的电荷。 第一极性电荷层设置在多个钝化层中的第一个和设置在光电二极管区域上的多个钝化层中的第二钝化层之间。

    CIRCUIT STRUCTURE FOR PROVIDING CONVERSION GAIN OF A PIXEL ARRAY
    18.
    发明申请
    CIRCUIT STRUCTURE FOR PROVIDING CONVERSION GAIN OF A PIXEL ARRAY 有权
    提供像素阵列转换增益的电路结构

    公开(公告)号：US20140231622A1

    公开(公告)日：2014-08-21

    申请号：US13773437

    申请日：2013-02-21

    Applicant: OmniVision Technologies, Inc.

    Inventor： Duli Mao ,  Vincent Venezia ,  Gang Chen ,  Hsin-Chih Tai ,  Howard Rhodes

    IPC: H04N5/335

    CPC classification number: H04N5/3559 ,  H01L27/14601 ,  H04N5/355 ,  H04N5/52

    Abstract: Techniques and mechanisms for a pixel array to provide a level of conversion gain. In an embodiment, the pixel array includes conversion gain control circuitry to be selectively configured at different times for different operational modes, each mode for implementing a respective conversion gain. The conversion gain control circuitry selectively provides switched coupling of the pixel cell to—and/or switched decoupling of the pixel cell from—a supply voltage. In another embodiment, the conversion gain control circuitry selectively provides switched coupling of the pixel cell to—and/or switched decoupling of the pixel cell from—sample and hold circuitry.

    Abstract translation: 像素阵列的技术和机制提供一个转换增益水平。 在一个实施例中，像素阵列包括转换增益控制电路，以在不同的时间针对不同的操作模式进行选择性地配置，每个模式用于实现相应的转换增益。 转换增益控制电路选择性地提供像素单元与像素单元与电源电压的 - 和/或开关去耦合的切换耦合。 在另一个实施例中，转换增益控制电路选择性地提供像素单元与采样和保持电路的 - 和/或开关去耦合的切换耦合。

    PAD DESIGN FOR CIRCUIT UNDER PAD IN SEMICONDUCTOR DEVICES
    19.
    发明申请
    PAD DESIGN FOR CIRCUIT UNDER PAD IN SEMICONDUCTOR DEVICES 有权
    用于在半导体器件中的电路下的电路的PAD设计

    公开(公告)号：US20140035089A1

    公开(公告)日：2014-02-06

    申请号：US14052944

    申请日：2013-10-14

    Applicant: OmniVision Technologies, Inc.

    Inventor： Yin Qian ,  Dyson H. Tai ,  Keh-Chiang Ku ,  Vincent Venezia ,  Duli Mao ,  Wei Zheng ,  Howard E. Rhodes

    IPC: H01L23/48

    CPC classification number: H01L23/481 ,  H01L21/6835 ,  H01L23/522 ,  H01L24/05 ,  H01L27/14636 ,  H01L27/1464 ,  H01L2221/6835 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05567 ,  H01L2924/00014 ,  H01L2924/12043 ,  H01L2224/05552 ,  H01L2924/00

    Abstract: Embodiments of a semiconductor device that includes a semiconductor substrate and a cavity disposed in the semiconductor substrate that extends at least from a first side of the semiconductor substrate to a second side of the semiconductor substrate. The semiconductor device also includes an insulation layer disposed over the first side of the semiconductor substrate and coating sidewalls of the cavity. A conductive layer including a bonding pad is disposed over the insulation layer. The conductive layer extends into the cavity and connects to a metal stack disposed below the second side of the semiconductor substrate. A through silicon via pad is disposed below the second side of the semiconductor substrate and connected to the metal stack. The through silicon via pad is position to accept a through silicon via.

    Abstract translation: 半导体器件的实施例包括半导体衬底和设置在半导体衬底中的至少从半导体衬底的第一侧至半导体衬底的第二侧延伸的空腔。 半导体器件还包括设置在半导体衬底的第一侧上并涂覆空腔的侧壁的绝缘层。 包括接合焊盘的导电层设置在绝缘层上。 导电层延伸到空腔中并且连接到设置在半导体衬底的第二侧下方的金属叠层。 贯穿硅通孔焊盘设置在半导体衬底的第二侧下方并连接到金属堆叠。 贯穿硅通孔焊盘的位置是接受硅通孔。

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