公开(公告)号：US20070133722A1

公开(公告)日：2007-06-14

申请号：US11538025

申请日：2006-10-02

申请人： Oscar Agazzi ,  Diego Crivelli ,  Hugo Carrer ,  Mario Hueda ,  German Luna

发明人： Oscar Agazzi ,  Diego Crivelli ,  Hugo Carrer ,  Mario Hueda ,  German Luna

IPC分类号： H03D1/04 ,  H03H7/30 ,  H03D1/00

CPC分类号： H04L25/03057 ,  H03M1/0626 ,  H03M1/1215 ,  H04L25/03184 ,  H04L25/03292 ,  H04L2025/03356 ,  H04L2025/03426 ,  H04L2025/03477 ,  H04L2025/03617

摘要： A system includes a time-interleaved device. An equalizer effectively can apply different equalization to different interleaved channels. For convenience, these equalizers will be referred to as multi-channel equalizers. In one aspect, an apparatus includes an interleaved device having M interleaved channels, and a multi-channel equalizer coupled to the interleaved device. The multi-channel equalizer is capable of applying a different equalization to different interleaved channels, thus compensating for channel-dependent impairments.

摘要翻译： 系统包括时间交织设备。 均衡器可以有效地将不同的均衡应用于不同的交织信道。 为了方便起见，这些均衡器将被称为多通道均衡器。 在一个方面，一种装置包括具有M个交织信道的交织设备和耦合到该交错设备的多信道均衡器。 多信道均衡器能够对不同的交织信道应用不同的均衡，从而补偿信道相关损伤。

公开(公告)号：US20060202755A1

公开(公告)日：2006-09-14

申请号：US11420406

申请日：2006-05-25

申请人： Arya Behzad ,  Klaas Bult ,  Ramon Gomez ,  Chi-Hung Lin ,  Tom Kwan ,  Oscar Agazzi ,  John Creigh ,  Mehdi Hatamian ,  David Kruse ,  Arthur Abnous ,  Henry Samueli

发明人： Arya Behzad ,  Klaas Bult ,  Ramon Gomez ,  Chi-Hung Lin ,  Tom Kwan ,  Oscar Agazzi ,  John Creigh ,  Mehdi Hatamian ,  David Kruse ,  Arthur Abnous ,  Henry Samueli

IPC分类号： H03F3/68

CPC分类号： H03F1/32 ,  H03F3/347 ,  H03F3/505 ,  H03F2200/211 ,  H03F2200/252 ,  H03F2200/421 ,  H03F2200/513 ,  H03G1/0088 ,  H03G3/001 ,  H03G3/3036 ,  H03G3/3052 ,  H03G5/10 ,  H03H11/245

摘要： Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal, By isolating the switches from the signal path linearity of the PGA can be improved.

摘要翻译： 电路从集成电路可编程增益衰减器中的信号路径中去除开关可编程增益衰减器和可编程增益放大器通常使用半导体开关在信号电平之间切换。 这种开关可能在信号中引入非线性。通过将开关与信号路径隔离，可以提高PGA的线性度。

公开(公告)号：US08363683B2

公开(公告)日：2013-01-29

申请号：US12805712

申请日：2010-08-16

申请人： Oscar Agazzi ,  Venugopal Gopinathan

发明人： Oscar Agazzi ,  Venugopal Gopinathan

IPC分类号： H04J3/06

CPC分类号： H04L25/03006 ,  H03M1/0604 ,  H03M1/0607 ,  H03M1/0609 ,  H03M1/0624 ,  H03M1/0836 ,  H03M1/1215 ,  H04B10/6933 ,  H04B10/697 ,  H04B10/6971 ,  H04L7/0054 ,  H04L7/0062 ,  H04L7/0337 ,  H04L25/03057 ,  H04L25/03133 ,  H04L25/03159 ,  H04L25/03203 ,  H04L2025/03445

摘要： Digital signal processing based methods and systems for receiving data signals include parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal. In an embodiment, a parallel DSP-based receiver in accordance with the invention includes a separate timing recovery loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate automatic gain control (AGC) loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate offset compensation loop for each ADC path. In an embodiment, the present invention is implemented as a multi-channel receiver that receives a plurality of data signals.

摘要翻译： 用于接收数据信号的基于数字信号处理的方法和系统包括并行接收机，多信道接收机，定时恢复方案，并且不限于均衡方案。 本发明被实现为多路径并行接收机，其中使用以比接收的数据信号更低的速率工作的并行路径来实现模数转换器（ADC）和/或数字信号处理器（DSP）。 在一个实施例中，根据本发明的基于并行DSP的接收机包括用于每个ADC路径的单独的定时恢复环路。 在一个实施例中，并行基于DSP的接收机包括用于每个ADC路径的单独的自动增益控制（AGC）环路。 在一个实施例中，并行基于DSP的接收机包括用于每个ADC路径的单独的偏移补偿环路。 在一个实施例中，本发明被实现为接收多个数据信号的多信道接收机。

公开(公告)号：US20080049826A1

公开(公告)日：2008-02-28

申请号：US11846195

申请日：2007-08-28

申请人： Oscar Agazzi ,  John Creigh ,  Mehdi Hatamian ,  David Kruse ,  Arthur Abnous ,  Henry Samueli

发明人： Oscar Agazzi ,  John Creigh ,  Mehdi Hatamian ,  David Kruse ,  Arthur Abnous ,  Henry Samueli

IPC分类号： H04L27/01 ,  H04B1/10

CPC分类号： H04L7/0062 ,  G01R31/3004 ,  G01R31/3008 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/318502 ,  G01R31/318552 ,  G01R31/318594 ,  H04B3/23 ,  H04B3/235 ,  H04B3/32 ,  H04L1/0021 ,  H04L1/0047 ,  H04L1/0053 ,  H04L1/0054 ,  H04L1/0059 ,  H04L1/006 ,  H04L1/242 ,  H04L7/0334 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03197 ,  H04L25/03203 ,  H04L25/03235 ,  H04L25/03267 ,  H04L25/03987 ,  H04L25/067 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/497 ,  H04L2001/0096 ,  H04L2025/03363 ,  H04L2025/03369 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03496 ,  H04L2025/03503 ,  H04L2025/03617 ,  H04L2025/03745

摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

摘要翻译： 公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。 基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。 通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。 生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。 调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

公开(公告)号：US20070263673A1

公开(公告)日：2007-11-15

申请号：US11826414

申请日：2007-07-16

申请人： Oscar Agazzi ,  Venugopal Gopinathan

发明人： Oscar Agazzi ,  Venugopal Gopinathan

IPC分类号： H04J3/06

CPC分类号： H04L25/03006 ,  H03M1/0604 ,  H03M1/0607 ,  H03M1/0609 ,  H03M1/0624 ,  H03M1/0836 ,  H03M1/1215 ,  H04B10/6933 ,  H04B10/697 ,  H04B10/6971 ,  H04L7/0054 ,  H04L7/0062 ,  H04L7/0337 ,  H04L25/03057 ,  H04L25/03133 ,  H04L25/03159 ,  H04L25/03203 ,  H04L2025/03445

摘要： Digital signal processing based methods and systems for receiving data signals include parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal. In an embodiment, a parallel DSP-based receiver in accordance with the invention includes a separate timing recovery loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate automatic gain control (AGC) loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate offset compensation loop for each ADC path. In an embodiment, the present invention is implemented as a multi-channel receiver that receives a plurality of data signals.

摘要翻译： 用于接收数据信号的基于数字信号处理的方法和系统包括并行接收机，多信道接收机，定时恢复方案，并且不限于均衡方案。 本发明被实现为多路径并行接收机，其中使用平行路径来实现模数转换器（“ADC”）和/或数字信号处理器（“DSP”），该路径以比 接收数据信号。 在一个实施例中，根据本发明的基于并行DSP的接收机包括用于每个ADC路径的单独的定时恢复环路。 在一个实施例中，并行基于DSP的接收机包括用于每个ADC路径的单独的自动增益控制（AGC）环路。 在一个实施例中，并行基于DSP的接收机包括用于每个ADC路径的单独的偏移补偿环路。 在一个实施例中，本发明被实现为接收多个数据信号的多信道接收机。

公开(公告)号：US20060245487A1

公开(公告)日：2006-11-02

申请号：US11257810

申请日：2005-10-25

申请人： Oscar Agazzi ,  David Kruse ,  Arthur Abnous ,  Mehdi Hatamian

发明人： Oscar Agazzi ,  David Kruse ,  Arthur Abnous ,  Mehdi Hatamian

IPC分类号： H03H7/30

CPC分类号： H04L7/0062 ,  G01R31/3004 ,  G01R31/3008 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/318502 ,  G01R31/318552 ,  G01R31/318594 ,  H03M13/256 ,  H03M13/41 ,  H03M13/6331 ,  H04B3/23 ,  H04B3/32 ,  H04L1/005 ,  H04L1/0052 ,  H04L1/0054 ,  H04L1/0059 ,  H04L1/242 ,  H04L7/0334 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03267 ,  H04L25/067 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/497 ,  H04L2025/03363 ,  H04L2025/03369 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03496 ,  H04L2025/03503 ,  H04L2025/03617 ,  H04L2025/03745

摘要： A method and a system for providing an input signal from a multiple decision feedback equalizer to a decoder based on a tail value and a subset of coefficient values received from a decision-feedback equalizer. A set of pre-computed values based on the subset of coefficient values is generated. Each of the pre-computed values is combined with the tail value to generate a tentative sample. One of the tentative samples is selected as the input signal to the decoder. In one aspect of the system, tentative samples are saturated and then stored in a set of registers before being outputted to a multiplexer which selects one of the tentative samples as the input signal to the decoder. This operation of storing the tentative samples in the registers before providing the tentative samples to the multiplexer facilitates high-speed operation by breaking up a critical path of computations into substantially balanced first and second portions, the first portion including computations in the decision-feedback equalizer and the multiple decision feedback equalizer, the second portion including computations in the decoder.

公开(公告)号：US20060238256A1

公开(公告)日：2006-10-26

申请号：US11417073

申请日：2006-05-02

申请人： Arya Behzad ,  Klaas Bult ,  Ramon Gomez ,  Chi-Hung Lin ,  Tom Kwan ,  Oscar Agazzi ,  John Creigh ,  Mehdi Hatamian ,  David Kruse ,  Arthur Abnous ,  Henry Samueli

发明人： Arya Behzad ,  Klaas Bult ,  Ramon Gomez ,  Chi-Hung Lin ,  Tom Kwan ,  Oscar Agazzi ,  John Creigh ,  Mehdi Hatamian ,  David Kruse ,  Arthur Abnous ,  Henry Samueli

IPC分类号： H03G3/00

CPC分类号： H03F1/32 ,  H03F3/347 ,  H03F3/505 ,  H03F2200/211 ,  H03F2200/252 ,  H03F2200/421 ,  H03F2200/513 ,  H03G1/0088 ,  H03G3/001 ,  H03G3/3036 ,  H03G3/3052 ,  H03G5/10 ,  H03H11/245

摘要： Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

公开(公告)号：US20050243903A1

公开(公告)日：2005-11-03

申请号：US11175715

申请日：2005-07-06

申请人： Oscar Agazzi

发明人： Oscar Agazzi

IPC分类号： G01R31/30 ,  G01R31/317 ,  G01R31/3185 ,  H03H7/30 ,  H03H21/00 ,  H04B1/38 ,  H04B3/23 ,  H04B3/32 ,  H04B3/46 ,  H04L1/00 ,  H04L1/08 ,  H04L1/24 ,  H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04L25/03 ,  H04L25/06 ,  H04L25/14 ,  H04L25/49 ,  H04L25/497 ,  H04L29/08

CPC分类号： H04L7/0062 ,  G01R31/3004 ,  G01R31/3008 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/318502 ,  G01R31/318552 ,  G01R31/318594 ,  H03H21/0067 ,  H03H2021/007 ,  H03H2021/0074 ,  H04B3/23 ,  H04B3/32 ,  H04B3/487 ,  H04L1/0009 ,  H04L1/0054 ,  H04L1/08 ,  H04L1/242 ,  H04L7/0334 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03267 ,  H04L25/067 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/497 ,  H04L69/323 ,  H04L2025/03363 ,  H04L2025/03369 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03496 ,  H04L2025/03503 ,  H04L2025/03617 ,  H04L2025/03681 ,  H04L2025/03745

摘要： A method for controlling operation of a multi-pair gigabit transceiver. The multi-pair gigabit transceiver comprises a Physical Layer Control module (PHY Control), a Physical Coding Sublayer module (PCS) and a Digital Signal Processing module (DSP). The PHY Control receives user-defined inputs from the Serial Management module and status signals and diagnostics signals from the DSP and the PCS and generates control signals, responsive to the user-defined inputs, the status signals and diagnostics signals, to the DSP and the PCS.

公开(公告)号：US20050189993A1

公开(公告)日：2005-09-01

申请号：US11005603

申请日：2004-12-06

申请人： Arya Behzad ,  Klaas Bult ,  Ramon Gomez ,  Chi-Hung Lin ,  Tom Kwan ,  Oscar Agazzi ,  John Creigh ,  Mehdi Hatamian ,  David Kruse ,  Arthur Abnous ,  Henry Samueli

发明人： Arya Behzad ,  Klaas Bult ,  Ramon Gomez ,  Chi-Hung Lin ,  Tom Kwan ,  Oscar Agazzi ,  John Creigh ,  Mehdi Hatamian ,  David Kruse ,  Arthur Abnous ,  Henry Samueli

IPC分类号： H03G1/00 ,  H03G3/00 ,  H03G3/30 ,  H03G5/10 ,  H03H11/24

CPC分类号： H03F1/32 ,  H03F3/347 ,  H03F3/505 ,  H03F2200/211 ,  H03F2200/252 ,  H03F2200/421 ,  H03F2200/513 ,  H03G1/0088 ,  H03G3/001 ,  H03G3/3036 ,  H03G3/3052 ,  H03G5/10 ,  H03H11/245

摘要： Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

摘要翻译： 电路从集成电路可编程增益衰减器中的信号路径中去除开关。 可编程增益衰减器和可编程增益放大器通常使用半导体开关在信号电平之间切换。 这种开关可能在信号中引入非线性。 通过将开关与信号路径隔离，可以提高PGA的线性度。

公开(公告)号：US20080101510A1

公开(公告)日：2008-05-01

申请号：US11968450

申请日：2008-01-02

申请人： Oscar Agazzi

发明人： Oscar Agazzi

IPC分类号： H04B1/10

CPC分类号： H04L7/0062 ,  H03M1/0624 ,  H03M1/0836 ,  H03M1/0863 ,  H03M1/1215 ,  H04B10/69 ,  H04L25/03057 ,  H04L25/03159 ,  H04L2025/03445

摘要： A DSP based SERDES performs compensation operations to support high speed de-serialization. A receiver section of the DSP based SERDES includes one or more ADCs and DSPs. The ADC operates to sample (modulated) analog serial data and to produce digitized serial data (digital representation of the modulated analog serial data). The DSP communicatively couples to the ADC and receives the digitized serial data. Based upon the known characteristics of the digitized serial data and the digitized serial data itself, the DSP determines compensation operations to be performed upon the serial data to compensate for inadequacies of the receiver and/or channel response. These compensation operations may be (1) performed on the analog serial data before digitization by the ADC; (2) applied to the ADC to modify the operation of the ADC; and/or (3) performed on the digitized serial data by the DSP or another device.

摘要翻译： 基于DSP的SERDES执行补偿操作以支持高速解除序列化。 基于DSP的SERDES的接收器部分包括一个或多个ADC和DSP。 ADC工作在采样（调制）模拟串行数据并产生数字化串行数据（调制模拟串行数据的数字表示）。 DSP通信耦合到ADC并接收数字化的串行数据。 基于数字化串行数据和数字化串行数据本身的已知特性，DSP确定要对串行数据执行的补偿操作，以补偿接收机和/或信道响应的不足。 这些补偿操作可以是（1）由ADC进行数字化之前对模拟串行数据执行的; （2）应用于ADC修改ADC的工作; 和/或（3）由DSP或另一设备对数字化的串行数据执行。