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公开(公告)号：US06208182B1
公开(公告)日：2001-03-27
申请号：US09184224
申请日：1998-11-02
Applicant: Roland Marbot , Guillaume Couzon
Inventor： Roland Marbot , Guillaume Couzon
IPC: H03L706
CPC classification number: H03K3/0315 , H03L7/091 , H03L7/0995
Abstract: The present invention relates to a phase-locked loop circuit including: a programmable ring oscillator generating drive signals, an assembly of latches receiving an input signal of the circuit, the latches being driven by the drive signals and generating samples by sampling of the input signal, and a logic decoding circuit receiving samples generated by latches and accordingly driving the oscillator.
Abstract translation: 本发明涉及一种锁相环电路，包括：产生驱动信号的可编程环形振荡器，接收电路输入信号的锁存器的组合，锁存器由驱动信号驱动，并通过对输入信号进行采样产生采样 以及逻辑解码电路，其接收由锁存器产生的采样并相应地驱动振荡器。
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公开(公告)号：US5521540A
公开(公告)日：1996-05-28
申请号：US451717
申请日：1995-05-26
Applicant: Roland Marbot
Inventor： Roland Marbot
IPC: H03K5/00 , H03K5/13 , H03K19/003 , H03H11/26
CPC classification number: H03K19/00361 , H03K5/131 , H03K5/133 , H03K2005/00065 , H03K2005/00195
Abstract: A method and apparatus for multi-range delay control is disclosed. A method furnishes an output signal (S.sub.K) with a delay that is variable with respect to an input signal (e.sub.0). To enable precise adjustment as a function of a set-point delay (CN) over a plurality of scales, a succession of signals (e.sub.1, e.sub.2, . . . , e.sub.n) delayed with respect to the input signal (e.sub.0) are produced, the delay between a delayed signal (e.sub.2) and the preceding signal (e.sub.1) having a predetermined value. One of the delayed signals (e.sub.2) and a preceding signal (e.sub.1) as selected and a superposition is performed with weighting and an integral effect of the selected signals (e.sub.1, e.sub.2), the selection and weighting being determined as a function of the set-point delay (CN).
Abstract translation: 公开了一种用于多范围延迟控制的方法和装置。 一种方法为输出信号（SK）提供相对于输入信号（e0）可变的延迟。 为了能够在多个刻度上作为设定点延迟（CN）的函数进行精确调整，产生相对于输入信号（e0）延迟的一系列信号（e1，e2，...，en） 延迟信号（e2）与前一信号（e1）之间的延迟具有预定值。 经选择的信号（e1，e2）的加权和积分效应执行选择的延迟信号（e2）和前一信号（e1）之一以及叠加，所述选择和加权被确定为集合的函数 点延迟（CN）。
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13.发明授权Variable delay circuit for producing a delay which varies as a hyperbolic function of the current intensity 失效用于产生随着当前强度的双曲线函数而变化的延迟的可变延迟电路
公开(公告)号：US5334891A
公开(公告)日：1994-08-02
申请号：US52279
申请日：1993-04-26
Applicant: Roland Marbot
Inventor： Roland Marbot
CPC classification number: H03H11/265
Abstract: The variable delay device 10 includes an ECL gate 11 associated with an adjusting circuit 23 acting on the resistance of resistive load elements 14, 15 of transistors 12, 13 and the resistive load element 18 of the current source 16 at the gate 11 to cause the current produced by the source 16 to vary linearly while keeping the voltage at the collectors of the transistors 12, 13 constant. The range of variation of the resistances is selected in such a way that the delay between the input signals IN, IN* and OUT, OUT* varies substantially linearly. The invention is particularly applicable to systems for digital data transmission at a very high rate, of more than 1 gigabit per second.
Abstract translation: 可变延迟装置10包括与调节电路23相关联的ECL门11，该调节电路23作用在栅极11处的晶体管12,13的电阻负载元件14,15的电阻和电流源16的电阻负载元件18， 源极16产生的电流线性变化，同时保持晶体管12,13的集电极处的电压恒定。 选择电阻的变化范围使得输入信号IN，IN *和OUT，OUT *之间的延迟基本上线性地变化。 本发明特别适用于以非常高的速率超过1吉比特/秒的数字数据传输系统。
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公开(公告)号：US5838178A
公开(公告)日：1998-11-17
申请号：US921334
申请日：1997-08-29
Applicant: Roland Marbot
Inventor： Roland Marbot
CPC classification number: H03B19/00 , H03B19/14 , H03K5/00006 , H03L7/0814 , H03L7/089 , H03L7/16
Abstract: The frequency multiplier 10 is embodied by a phase-locked loop including a phase comparator 11 for commanding a plurality of delay elements 130 to 137 that furnish successive phase-shifted signals CL0-CL7 to a logical adder 16 made up of EXCLUSIVE OR gates.
Abstract translation: 倍频器10由包括相位比较器11的锁相环实现，该相位比较器11用于指令多个延迟元件130至137，延迟元件130至137将连续的相移信号CL0-CL7提供给由“独占或”门构成的逻辑加法器16。
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公开(公告)号：US5430773A
公开(公告)日：1995-07-04
申请号：US161698
申请日：1993-12-06
Applicant: Roland Marbot
Inventor： Roland Marbot
CPC classification number: H04L7/0337 , H04L7/044 , H04L7/048
Abstract: The apparatus for sampling data recurring with a period (R) in the data signal (TS) includes a phasing circuit (43) that adjusts the delay of a clock signal with respect to one edge of the data signal to a value (n+.alpha.) R, where n is a positive integer or 0, and .alpha. is a positive number less than 1. The invention applies in particular to digital data transmission network systems, and in particular to information processing systems.
Abstract translation: 用于对在数据信号（TS）中的周期（R）重复的数据进行采样的设备包括相位电路（43），其将相对于数据信号的一个边缘的时钟信号的延迟调整为值（n +α） R，其中n是正整数或0，α是小于1的正数。本发明特别适用于数字数据传输网络系统，特别是涉及信息处理系统。
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Patent Agency Ranking16.发明授权Apparatus for serialization and deserialization of data, and resultant system for digital transmission of serial data 失效用于串行化和反序列化数据的装置，以及用于串行数据的数字传输的结果系统
公开(公告)号：US5414830A
公开(公告)日：1995-05-09
申请号：US727429
申请日：1991-07-09
Applicant: Roland Marbot
Inventor： Roland Marbot
Abstract: The apparatus 15 for serialization of words of N bits SYNC, OP, D0-D7 produces N clock signals CL0-CL9 of period T, delayed successively by T/N, to control respective registers (36, 38, 39) for the successive output of the bits of each word. An adder (40) reunites these bits in a serial data transmission signal (TS). The deserialization is applicable in particular to network transmission systems, and especially to information processing systems.
Abstract translation: 用于串行化N位SYNC，OP，D0-D7的字的装置15产生周期T的N个时钟信号CL0-CL9，其连续延迟T / N，以控制相应的寄存器（36,38,39），用于连续输出 的每一个字的位。 加法器（40）在串行数据传输信号（TS）中重新统一这些位。 反序列化特别适用于网络传输系统，尤其适用于信息处理系统。
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17.发明授权Process and circuit for detecting transmission using bi-directional differential links 失效使用双向差分链路检测传输的过程和电路
公开(公告)号：US5412688A
公开(公告)日：1995-05-02
申请号：US199354
申请日：1994-02-18
Applicant: Roland Marbot
Inventor： Roland Marbot
CPC classification number: H03K5/026 , H04B1/58 , H04L5/1423
Abstract: In certain bidirectional transmissions, differential links (L, L*) are used and transceivers (1) that furnish differential measurement signals (V, V*) representative of the transmission signals of the remote station are used. To reduce power consumption, the electrical power to the transceivers (1) may be interrupted during periods of inactivity. The method of the present invention consists in determining a threshold value which is intermediate in value between the maximum and minimum values that can be assumed by the measurement signals (V, V*), and furnishing a signal (VAL) representative of transmission activity resulting from the comparison between the measurement signals (V, V*) and the threshold value. The circuit for employing the method uses voltage comparators and may be an integrated circuit.
Abstract translation: 在某些双向传输中，使用差分链路（L，L *），并且使用提供表示远程站的传输信号的差分测量信号（V，V *）的收发器（1）。 为了降低功耗，收发器（1）的电力可能在不活动期间中断。 本发明的方法在于确定在测量信号（V，V *）可以假设的最大值和最小值之间的中间值的阈值，并提供表示传输活动的信号（VAL） 从测量信号（V，V *）和阈值之间的比较。 采用该方法的电路使用电压比较器，并且可以是集成电路。
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18.发明申请公开(公告)号：US20070043979A1
公开(公告)日：2007-02-22
申请号：US11509304
申请日：2006-08-23
Applicant: Gerard Humeau , Roland Marbot
Inventor： Gerard Humeau , Roland Marbot
IPC: G06F11/00
CPC classification number: G06F11/3636
Abstract: A method for monitoring the execution of a program by a processor of an electronic circuit comprises operations of collecting monitoring data within the circuit and of transmitting the monitoring data to a device for debugging the program. The monitoring data are transmitted via a connection external to the circuit, comprising at least one serial connection. The monitoring data are serialized within the circuit before being transmitted, then restored within the device for tuning the program.
Abstract translation: 一种用于监视由电子电路的处理器执行程序的方法包括收集电路内的监视数据并将监视数据发送到用于调试程序的设备的操作。 监视数据经由电路外部的连接发送，包括至少一个串行连接。 监控数据在发送之前在电路内串行化，然后在设备内恢复以调谐程序。
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公开(公告)号：US06975173B2
公开(公告)日：2005-12-13
申请号：US10662180
申请日：2003-09-12
Applicant: Roland Marbot , Franck Hellard
Inventor： Roland Marbot , Franck Hellard
CPC classification number: H03K5/26 , H03K5/133 , H03K5/135 , H03K2005/00058 , H03L7/0812 , H04L7/0338
Abstract: A device for transforming a periodic input signal into an output signal of distinct frequency, comprising two adjustable delay means receiving the input signal, a multiplexer selecting the output signal of one or the other of the delay means, control means for, according to whether the output signal frequency must be smaller or greater than the input signal frequency, increasing or decreasing at the rate of the input signal, or at a multiple of this rate, the delay of the selected delay means, and controlling a minimum or maximum delay for the delay means which has not been selected, and a phase comparator adapted to changing the multiplexer selection when the transitions of the signals output by the delay means corresponding to a same transition of the input signal are offset by a duration greater than or equal to one period of the input signal.
Abstract translation: 一种用于将周期性输入信号变换为不同频率的输出信号的装置，包括接收输入信号的两个可调延迟装置，选择延迟装置中的一个或另一个的输出信号的多路复用器，根据是否 输出信号频率必须小于或大于输入信号频率，以输入信号的速率增加或减小，或以该速率的倍数，所选择的延迟装置的延迟，并且控制最小或最大延迟 延迟装置，以及相位比较器，适于在延迟装置输出的对应于输入信号的相同转变的信号的转变偏移持续时间大于或等于一个周期的情况下改变多路复用器选择 的输入信号。
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20.发明授权Three-dimensional integrated circuit package having conductors at different fixed potentials 失效具有不同固定电位导体的三维集成电路封装
公开(公告)号：US5925925A
公开(公告)日：1999-07-20
申请号：US833060
申请日：1997-04-03
Applicant: Gerard Dehaine , Roland Marbot , Michel Moreau , Yves Stricot
Inventor： Gerard Dehaine , Roland Marbot , Michel Moreau , Yves Stricot
IPC: H01L23/50 , H01L23/66 , H01L23/552 , H01L23/04 , H01L23/52
CPC classification number: H01L24/48 , H01L23/66 , H01L24/49 , H01L2224/05599 , H01L2224/48091 , H01L2224/48472 , H01L2224/49109 , H01L2224/49175 , H01L2224/4943 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01014 , H01L2924/01019 , H01L2924/01033 , H01L2924/01058 , H01L2924/01061 , H01L2924/01078 , H01L2924/01082 , H01L2924/01094 , H01L2924/014 , H01L2924/14 , H01L2924/15173 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/30111 , H01L2924/3025
Abstract: The invention applies to packages for transmitting signals at very high frequencies. A package (10) for the integrated circuit (11) comprises conductors disposed on at least two levels (N1-N6) and distributed so that two pairs of conductors of two fixed potentials (18d, 18g; 19d, 19g), along with a conductor (18s) for single-pole transmission of a signal, form a three-dimensional structure which is approximately coaxial having a characteristic impedance which is substantially constant and predetermined.
Abstract translation: 本发明适用于以非常高的频率传输信号的封装。 用于集成电路（11）的封装（10）包括设置在至少两个级（N1-N6）上的导体，并分布成使得两对固定电位的导体（18d，18g，19d，19g）连同一个 导体（18s）用于信号的单极传输，形成近似同轴的具有基本恒定和预定的特性阻抗的三维结构。
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