公开(公告)号：US20140001549A1

公开(公告)日：2014-01-02

申请号：US13671506

申请日：2012-11-07

申请人： HUBERT M. BODE ,  Weize Chen ,  Richard J. De Souza ,  Patrice M. Parris

发明人： HUBERT M. BODE ,  Weize Chen ,  Richard J. De Souza ,  Patrice M. Parris

IPC分类号： H01L27/04 ,  H01L21/02

CPC分类号： H01L27/04 ,  H01L21/02381 ,  H01L21/761 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7817 ,  H01L29/7835

摘要： Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within a portion of the substrate contained by the isolation structure, and a resistor circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a body region, which is separated from the isolation structure by a portion of the semiconductor substrate having the first conductivity type. The resistor circuit is connected between the isolation structure and the body region. The resistor circuit may include one or more resistor networks and, optionally, a Schottky diode and/or one or more PN diode(s) in series and/or parallel with the resistor network(s).

摘要翻译： 半导体器件和驱动器电路的实施例包括具有第一导电类型的半导体衬底，隔离结构（包括沉陷区和掩埋层），由隔离结构包含的衬底的一部分内的有源器件，以及电阻器电路 。 掩埋层位于顶部衬底表面下方，并且具有第二导电类型。 沉降片区域在顶部衬底表面和掩埋层之间延伸，并且具有第二导电类型。 有源器件包括主体区域，其通过具有第一导电类型的半导体衬底的一部分与隔离结构分离。 电阻电路连接在隔离结构和体区之间。 电阻器电路可以包括一个或多个电阻器网络，以及可选地与电阻器网络串联和/或并联的肖特基二极管和/或一个或多个PN二极管。

公开(公告)号：US09991356B2

公开(公告)日：2018-06-05

申请号：US15246262

申请日：2016-08-24

申请人： Weize Chen ,  Richard J. de Souza ,  Md M. Hoque ,  Patrice M. Parris

发明人： Weize Chen ,  Richard J. de Souza ,  Md M. Hoque ,  Patrice M. Parris

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8234

CPC分类号： H01L29/4933 ,  H01L21/28052 ,  H01L21/28105 ,  H01L21/823443 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/4983 ,  H01L29/66477 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

摘要： Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel. The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices.

公开(公告)号：US09236472B2

公开(公告)日：2016-01-12

申请号：US13448994

申请日：2012-04-17

申请人： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

发明人： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L29/7823 ,  H01L21/2253 ,  H01L29/0626 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7824 ,  H01L29/7835

摘要： A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path.

摘要翻译： 一种器件包括具有第一导电类型的半导体衬底，半导体衬底中的器件隔离区，限定有源区，并具有第二导电类型，有源区中的体区，并具有第一导电类型，漏极 区域，并且与身体区域间隔开以限定器件的导电路径，漏极区域具有第二导电类型。 器件隔离区域和体区域彼此间隔开以建立低于导通路径中的第二击穿电压的第一击穿电压。

公开(公告)号：US09024380B2

公开(公告)日：2015-05-05

申请号：US13529589

申请日：2012-06-21

申请人： Weize Chen ,  Richard J. De Souza ,  Patrice M. Parris

发明人： Weize Chen ,  Richard J. De Souza ,  Patrice M. Parris

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/0692 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/66659 ,  H01L29/7835

摘要： A device includes a semiconductor substrate, a body region in the semiconductor substrate, having a first conductivity type, and including a channel region through which charge carriers flow, a drain region in the semiconductor substrate, having a second conductivity type, and spaced from the body region along a first lateral dimension, a drift region in the semiconductor substrate, having the second conductivity type, and electrically coupling the drain region to the channel region, and a plurality of floating reduced surface field (RESURF) regions in the semiconductor substrate adjacent the drift region, having the first conductivity type, and around which the charge carriers drift through the drift region under an electric field arising from a voltage applied to the drain region. Adjacent floating RESURF regions of the plurality of floating RESURF regions are spaced from one another along a second lateral dimension of the device by a respective gap.

摘要翻译： 一种器件包括半导体衬底，半导体衬底中的主体区域，具有第一导电类型，并且包括电荷载流子流过的沟道区域，半导体衬底中的漏极区域，具有第二导电类型，并与第二导电类型间隔开 沿着第一横向尺寸的主体区域，具有第二导电类型的半导体衬底中的漂移区域，以及将漏极区域电耦合到沟道区域，以及在半导体衬底相邻的多个浮动缩小表面场（RESURF）区域 具有第一导电类型的漂移区域，并且电荷载流子在由施加到漏极区域的电压产生的电场下漂移穿过漂移区域。 多个浮动RESURF区域的相邻的浮动RESURF区域沿设备的第二横向尺寸彼此间隔开。

公开(公告)号：US20110299337A1

公开(公告)日：2011-12-08

申请号：US12794591

申请日：2010-06-04

申请人： Patrice M. Parris ,  Weize Chen ,  Richard J. De Souza ,  Md M. Hoque ,  John M. McKenna

发明人： Patrice M. Parris ,  Weize Chen ,  Richard J. De Souza ,  Md M. Hoque ,  John M. McKenna

IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L27/108

CPC分类号： G01N27/4148 ,  G05F1/575 ,  G11C16/0416 ,  H01L21/28035 ,  H01L23/5223 ,  H01L27/11526 ,  H01L27/11558 ,  H01L28/40 ,  H01L28/60 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.

摘要翻译： ISFET包括耦合到CMOS器件中的浮动栅极的控制栅极。 控制栅极，例如多孔阱电容器被配置为接收偏置电压并且在控制栅极和浮置栅极之间实现俘获电荷的移动。 因此，ISFET的阈值电压可以被修整到预定值，从而将修剪信息（浮置栅极中的俘获电荷的量）存储在ISFET本身内。

公开(公告)号：US20160365422A1

公开(公告)日：2016-12-15

申请号：US15246262

申请日：2016-08-24

申请人： Weize Chen ,  Richard J. de Souza ,  Md M. Hoque ,  Patrice M. Parris

发明人： Weize Chen ,  Richard J. de Souza ,  Md M. Hoque ,  Patrice M. Parris

IPC分类号： H01L29/49 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/06

CPC分类号： H01L29/4933 ,  H01L21/28052 ,  H01L21/28105 ,  H01L21/823443 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/4983 ,  H01L29/66477 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

摘要： Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices.

摘要翻译： 具有反掺杂导电栅极的集成电路器件。 这些器件具有具有衬底表面的半导体衬底。 器件还具有第一导电类型的第一阱，第二导电类型的源极和第二导电类型的漏极。 通道在源极和漏极之间延伸。 导电栅极延伸穿过沟道。导电栅极包括第一导电类型的第一栅极区域和第二栅极区域以及第一导电类型的第三栅极区域。 第三栅极区域在第一和第二栅极区域之间延伸。 器件还包括在导电栅极和衬底之间延伸并且还包括与第一，第二和第三栅极区域电连通的硅化物区域的栅极电介质。 这些方法包括制造器件的方法。

公开(公告)号：US20160356740A1

公开(公告)日：2016-12-08

申请号：US14731795

申请日：2015-06-05

申请人： Patrice M. Parris ,  Weize Chen ,  Richard J. de Souza ,  Jose Fernandez Villasenor ,  Md M. Hoque ,  David E. Niewolny ,  Raymond M. Roop

发明人： Patrice M. Parris ,  Weize Chen ,  Richard J. de Souza ,  Jose Fernandez Villasenor ,  Md M. Hoque ,  David E. Niewolny ,  Raymond M. Roop

IPC分类号： G01N27/414 ,  B01L3/00

CPC分类号： G01N27/4148 ,  B01L3/5027 ,  B01L3/502715 ,  B01L3/50273 ,  B01L2200/10 ,  B01L2200/12 ,  B01L2300/04 ,  B01L2300/041 ,  B01L2300/0645 ,  B01L2300/0887 ,  B01L2400/0415 ,  B01L2400/0418 ,  G01N27/28 ,  G01N27/414 ,  H01L21/67259 ,  H01L29/4933 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7833 ,  H01L31/119

摘要： Protected sensor field effect transistors (SFETs). The SFETs include a semiconductor substrate, a field effect transistor, and a sense electrode. The SFETs further include an analyte-receiving region that is supported by the semiconductor substrate, is in contact with the sense electrode, and is configured to receive an analyte fluid. The analyte-receiving region is at least partially enclosed. In some embodiments, the analyte-receiving region can be an enclosed analyte channel that extends between an analyte inlet and an analyte outlet. In these embodiments, the enclosed analyte channel extends such that the analyte inlet and the analyte outlet are spaced apart from the sense electrode. In some embodiments, the SFETs include a cover structure that at least partially encloses the analyte-receiving region and is formed from a cover material that is soluble within the analyte fluid. The methods include methods of manufacturing the SFETs.

公开(公告)号：US09142554B2

公开(公告)日：2015-09-22

申请号：US13671503

申请日：2012-11-07

申请人： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

发明人： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

IPC分类号： H01L29/78 ,  H01L21/76 ,  H01L27/07 ,  H01L21/761

CPC分类号： H01L27/0727 ,  H01L21/761 ,  H01L29/66143 ,  H01L29/66681

摘要： Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a body region of the second conductivity type, and the diode circuit is connected between the isolation structure and the body region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s).

摘要翻译： 半导体器件和驱动电路的实施例包括具有第一导电类型的半导体衬底，隔离结构（包括沉陷区和掩埋层），由隔离结构包含的衬底区域内的有源器件和二极管电路。 掩埋层位于顶部衬底表面下方，并且具有第二导电类型。 沉降片区域在顶部衬底表面和掩埋层之间延伸，并且具有第二导电类型。 有源器件包括第二导电类型的体区，并且二极管电路连接在隔离结构和体区之间。 二极管电路可以包括一个或多个肖特基二极管和/或PN结二极管。 在另外的实施例中，二极管电路可以包括与肖特基和/或PN二极管串联和/或并联的一个或多个电阻网络。

公开(公告)号：US09111767B2

公开(公告)日：2015-08-18

申请号：US13538565

申请日：2012-06-29

申请人： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

发明人： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

IPC分类号： H01L27/088 ,  H01L21/02 ,  H01L27/06 ,  H01L29/861 ,  H01L29/872

CPC分类号： H01L27/0629 ,  H01L27/0288 ,  H01L29/04 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66681 ,  H01L29/7818 ,  H01L29/782 ,  H01L29/861 ,  H01L29/872

摘要： Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a source region of the first conductivity type, and the diode circuit is connected between the isolation structure and the source region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s).

摘要翻译： 半导体器件和驱动电路的实施例包括具有第一导电类型的半导体衬底，隔离结构（包括沉陷区和掩埋层），由隔离结构包含的衬底区域内的有源器件和二极管电路。 掩埋层位于顶部衬底表面下方，并且具有第二导电类型。 沉降片区域在顶部衬底表面和掩埋层之间延伸，并且具有第二导电类型。 有源器件包括第一导电类型的源极区域，二极管电路连接在隔离结构和源极区域之间。 二极管电路可以包括一个或多个肖特基二极管和/或PN结二极管。 在另外的实施例中，二极管电路可以包括与肖特基和/或PN二极管串联和/或并联的一个或多个电阻网络。

公开(公告)号：US20130341717A1

公开(公告)日：2013-12-26

申请号：US13529589

申请日：2012-06-21

申请人： Weize Chen ,  Richard J. De Souza ,  Patrice M. Parris

发明人： Weize Chen ,  Richard J. De Souza ,  Patrice M. Parris

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0692 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/66659 ,  H01L29/7835

摘要： A device includes a semiconductor substrate, a body region in the semiconductor substrate, having a first conductivity type, and including a channel region through which charge carriers flow, a drain region in the semiconductor substrate, having a second conductivity type, and spaced from the body region along a first lateral dimension, a drift region in the semiconductor substrate, having the second conductivity type, and electrically coupling the drain region to the channel region, and a plurality of floating reduced surface field (RESURF) regions in the semiconductor substrate adjacent the drift region, having the first conductivity type, and around which the charge carriers drift through the drift region under an electric field arising from a voltage applied to the drain region. Adjacent floating RESURF regions of the plurality of floating RESURF regions are spaced from one another along a second lateral dimension of the device by a respective gap.

摘要翻译： 一种器件包括半导体衬底，半导体衬底中的主体区域，具有第一导电类型，并且包括电荷载流子流过的沟道区域，半导体衬底中的漏极区域，具有第二导电类型，并与第二导电类型间隔开 沿着第一横向尺寸的主体区域，具有第二导电类型的半导体衬底中的漂移区域，以及将漏极区域电耦合到沟道区域，以及在半导体衬底相邻的多个浮动缩小表面场（RESURF）区域 具有第一导电类型的漂移区域，并且电荷载流子在由施加到漏极区域的电压产生的电场下漂移穿过漂移区域。 多个浮动RESURF区域的相邻的浮动RESURF区域沿设备的第二横向尺寸彼此间隔开。