公开(公告)号：US20130270606A1

公开(公告)日：2013-10-17

申请号：US13448994

申请日：2012-04-17

申请人： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

发明人： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

IPC分类号： H01L29/06 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7823 ,  H01L21/2253 ,  H01L29/0626 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7824 ,  H01L29/7835

摘要： A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path.

摘要翻译： 一种器件包括具有第一导电类型的半导体衬底，半导体衬底中的器件隔离区，限定有源区，并具有第二导电类型，有源区中的体区，并具有第一导电类型，漏极 区域，并且与身体区域间隔开以限定器件的导电路径，漏极区域具有第二导电类型。 器件隔离区域和体区域彼此间隔开以建立低于导通路径中的第二击穿电压的第一击穿电压。

公开(公告)号：US09236472B2

公开(公告)日：2016-01-12

申请号：US13448994

申请日：2012-04-17

申请人： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

发明人： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L29/7823 ,  H01L21/2253 ,  H01L29/0626 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7824 ,  H01L29/7835

摘要： A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path.

摘要翻译： 一种器件包括具有第一导电类型的半导体衬底，半导体衬底中的器件隔离区，限定有源区，并具有第二导电类型，有源区中的体区，并具有第一导电类型，漏极 区域，并且与身体区域间隔开以限定器件的导电路径，漏极区域具有第二导电类型。 器件隔离区域和体区域彼此间隔开以建立低于导通路径中的第二击穿电压的第一击穿电压。

公开(公告)号：US20140001549A1

公开(公告)日：2014-01-02

申请号：US13671506

申请日：2012-11-07

申请人： HUBERT M. BODE ,  Weize Chen ,  Richard J. De Souza ,  Patrice M. Parris

发明人： HUBERT M. BODE ,  Weize Chen ,  Richard J. De Souza ,  Patrice M. Parris

IPC分类号： H01L27/04 ,  H01L21/02

CPC分类号： H01L27/04 ,  H01L21/02381 ,  H01L21/761 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7817 ,  H01L29/7835

摘要： Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within a portion of the substrate contained by the isolation structure, and a resistor circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a body region, which is separated from the isolation structure by a portion of the semiconductor substrate having the first conductivity type. The resistor circuit is connected between the isolation structure and the body region. The resistor circuit may include one or more resistor networks and, optionally, a Schottky diode and/or one or more PN diode(s) in series and/or parallel with the resistor network(s).

摘要翻译： 半导体器件和驱动器电路的实施例包括具有第一导电类型的半导体衬底，隔离结构（包括沉陷区和掩埋层），由隔离结构包含的衬底的一部分内的有源器件，以及电阻器电路 。 掩埋层位于顶部衬底表面下方，并且具有第二导电类型。 沉降片区域在顶部衬底表面和掩埋层之间延伸，并且具有第二导电类型。 有源器件包括主体区域，其通过具有第一导电类型的半导体衬底的一部分与隔离结构分离。 电阻电路连接在隔离结构和体区之间。 电阻器电路可以包括一个或多个电阻器网络，以及可选地与电阻器网络串联和/或并联的肖特基二极管和/或一个或多个PN二极管。

公开(公告)号：US09142554B2

公开(公告)日：2015-09-22

申请号：US13671503

申请日：2012-11-07

申请人： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

发明人： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

IPC分类号： H01L29/78 ,  H01L21/76 ,  H01L27/07 ,  H01L21/761

CPC分类号： H01L27/0727 ,  H01L21/761 ,  H01L29/66143 ,  H01L29/66681

摘要： Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a body region of the second conductivity type, and the diode circuit is connected between the isolation structure and the body region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s).

摘要翻译： 半导体器件和驱动电路的实施例包括具有第一导电类型的半导体衬底，隔离结构（包括沉陷区和掩埋层），由隔离结构包含的衬底区域内的有源器件和二极管电路。 掩埋层位于顶部衬底表面下方，并且具有第二导电类型。 沉降片区域在顶部衬底表面和掩埋层之间延伸，并且具有第二导电类型。 有源器件包括第二导电类型的体区，并且二极管电路连接在隔离结构和体区之间。 二极管电路可以包括一个或多个肖特基二极管和/或PN结二极管。 在另外的实施例中，二极管电路可以包括与肖特基和/或PN二极管串联和/或并联的一个或多个电阻网络。

公开(公告)号：US09111767B2

公开(公告)日：2015-08-18

申请号：US13538565

申请日：2012-06-29

申请人： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

发明人： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

IPC分类号： H01L27/088 ,  H01L21/02 ,  H01L27/06 ,  H01L29/861 ,  H01L29/872

CPC分类号： H01L27/0629 ,  H01L27/0288 ,  H01L29/04 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66681 ,  H01L29/7818 ,  H01L29/782 ,  H01L29/861 ,  H01L29/872

摘要： Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a source region of the first conductivity type, and the diode circuit is connected between the isolation structure and the source region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s).

摘要翻译： 半导体器件和驱动电路的实施例包括具有第一导电类型的半导体衬底，隔离结构（包括沉陷区和掩埋层），由隔离结构包含的衬底区域内的有源器件和二极管电路。 掩埋层位于顶部衬底表面下方，并且具有第二导电类型。 沉降片区域在顶部衬底表面和掩埋层之间延伸，并且具有第二导电类型。 有源器件包括第一导电类型的源极区域，二极管电路连接在隔离结构和源极区域之间。 二极管电路可以包括一个或多个肖特基二极管和/或PN结二极管。 在另外的实施例中，二极管电路可以包括与肖特基和/或PN二极管串联和/或并联的一个或多个电阻网络。

公开(公告)号：US20140001548A1

公开(公告)日：2014-01-02

申请号：US13671503

申请日：2012-11-07

申请人： WEIZE CHEN ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

发明人： WEIZE CHEN ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

IPC分类号： H01L29/78 ,  H01L21/76

CPC分类号： H01L27/0727 ,  H01L21/761 ,  H01L29/66143 ,  H01L29/66681

摘要： Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a body region of the second conductivity type, and the diode circuit is connected between the isolation structure and the body region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s).

摘要翻译： 半导体器件和驱动电路的实施例包括具有第一导电类型的半导体衬底，隔离结构（包括沉陷区和掩埋层），由隔离结构包含的衬底区域内的有源器件和二极管电路。 掩埋层位于顶部衬底表面下方，并且具有第二导电类型。 沉降片区域在顶部衬底表面和掩埋层之间延伸，并且具有第二导电类型。 有源器件包括第二导电类型的体区，并且二极管电路连接在隔离结构和体区之间。 二极管电路可以包括一个或多个肖特基二极管和/或PN结二极管。 在另外的实施例中，二极管电路可以包括与肖特基和/或PN二极管串联和/或并联的一个或多个电阻网络。

公开(公告)号：US09704853B2

公开(公告)日：2017-07-11

申请号：US13671506

申请日：2012-11-07

申请人： Hubert M. Bode ,  Weize Chen ,  Richard J. De Souza ,  Patrice M. Parris

发明人： Hubert M. Bode ,  Weize Chen ,  Richard J. De Souza ,  Patrice M. Parris

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L27/06 ,  H01L21/761 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L27/092

CPC分类号： H01L27/04 ,  H01L21/02381 ,  H01L21/761 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7817 ,  H01L29/7835

摘要： Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within a portion of the substrate contained by the isolation structure, and a resistor circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a body region, which is separated from the isolation structure by a portion of the semiconductor substrate having the first conductivity type. The resistor circuit is connected between the isolation structure and the body region. The resistor circuit may include one or more resistor networks and, optionally, a Schottky diode and/or one or more PN diode(s) in series and/or parallel with the resistor network(s).

公开(公告)号：US09129990B2

公开(公告)日：2015-09-08

申请号：US13538529

申请日：2012-06-29

申请人： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

发明人： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

IPC分类号： H01L27/088 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L27/06 ,  H01L21/761 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H03K17/687 ,  H03K17/74

CPC分类号： H01L21/823481 ,  H01L21/761 ,  H01L21/823418 ,  H01L27/0629 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66659 ,  H01L29/7835 ,  H03K17/6871 ,  H03K17/74 ,  H03K2217/0018 ,  H03K2217/0036

摘要： Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a drain region of the second conductivity type, and the diode circuit is connected between the isolation structure and the drain region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s).

摘要翻译： 半导体器件和驱动电路的实施例包括具有第一导电类型的半导体衬底，隔离结构（包括沉陷区和掩埋层），由隔离结构包含的衬底区域内的有源器件和二极管电路。 掩埋层位于顶部衬底表面下方，并且具有第二导电类型。 沉降片区域在顶部衬底表面和掩埋层之间延伸，并且具有第二导电类型。 有源器件包括第二导电类型的漏极区域，二极管电路连接在隔离结构和漏极区域之间。 二极管电路可以包括一个或多个肖特基二极管和/或PN结二极管。 在另外的实施例中，二极管电路可以包括与肖特基和/或PN二极管串联和/或并联的一个或多个电阻网络。

公开(公告)号：US20150316503A1

公开(公告)日：2015-11-05

申请号：US14265622

申请日：2014-04-30

申请人： Md M. Hoque ,  Patrice M. Parris ,  Weize Chen ,  Richard J. De Souza

发明人： Md M. Hoque ,  Patrice M. Parris ,  Weize Chen ,  Richard J. De Souza

IPC分类号： G01N27/414 ,  H01L29/78 ,  H01L29/66

CPC分类号： G01N27/4148 ,  H01L21/28282 ,  H01L27/11531 ,  H01L29/66 ,  H01L29/66409 ,  H01L29/78 ,  H01L29/788

摘要： A differential pair sensing circuit (300) includes control gates (306, 316) for separately programming a reference transistor (350) and a chemically-sensitive transistor (351) to a desired threshold voltage Vt to eliminate the mismatch between the transistors in order to increase the sensitivity and/or accuracy of the sensing circuit without increasing the circuit size.

摘要翻译： 差分对检测电路（300）包括用于将参考晶体管（350）和化学敏感晶体管（351）单独编程为期望阈值电压Vt的控制栅极（306,316），以消除晶体管之间的失配，以便 提高感测电路的灵敏度和/或精度，而不增加电路尺寸。

公开(公告)号：US08344443B2

公开(公告)日：2013-01-01

申请号：US12109736

申请日：2008-04-25

申请人： Weize Chen ,  Richard J. De Souza ,  Xin Lin ,  Patrice M. Parris

发明人： Weize Chen ,  Richard J. De Souza ,  Xin Lin ,  Patrice M. Parris

IPC分类号： H01L29/788 ,  H01L27/115 ,  H01L21/8247

CPC分类号： H01L29/7881 ,  G11C16/10 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42324

摘要： A single-poly non-volatile memory includes a PMOS select transistor (210) formed with a select gate (212), and P+ source and drain regions (211, 213) formed in a shared n-well region (240), a serially connected PMOS floating gate transistor (220) formed with part of a p-type floating gate layer (222) and P+ source and drain regions (221, 223) formed in the shared n-well region (240), and a coupling capacitor (230) formed over a p-well region (250) and connected to the PMOS floating gate transistor (220), where the coupling capacitor (230) includes a first capacitor plate formed with a second part of the p-type floating gate layer (222) and an underlying portion of the p-well region (250).

摘要翻译： 单多晶非易失性存储器包括形成有选择栅极（212）的PMOS选择晶体管（210），以及形成在共享的n阱区域（240）中的P +源区和漏区（211,213） 形成有形成在共用n阱区域（240）中的p型浮栅（222）和P +源区和漏区（221,223）的一部分的连接PMOS浮栅晶体管（220）和耦合电容器 230），其形成在p阱区（250）上并连接到PMOS浮栅晶体管（220），其中耦合电容器（230）包括形成有p型浮栅的第二部分的第一电容器板（ 222）和p阱区（250）的下层部分。