公开(公告)号：US07667980B2

公开(公告)日：2010-02-23

申请号：US11539990

申请日：2006-10-10

Applicant: Brian A. Baker ,  James E. Hughes ,  Thomas D. Pahel, Jr. ,  Pravin Patel ,  Challis L. Purrington ,  Christopher C. West

Inventor： Brian A. Baker ,  James E. Hughes ,  Thomas D. Pahel, Jr. ,  Pravin Patel ,  Challis L. Purrington ,  Christopher C. West

IPC: H05K7/00

CPC classification number: H05K1/0216 ,  H05K1/0231 ,  H05K1/0233 ,  H05K3/429 ,  H05K2201/0792 ,  H05K2201/09318 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/1003

Abstract: Printed circuit boards for countering signal distortion are disclosed that include: a conductive pathway on a printed circuit board between a transmitter and a receiver, the conductive pathway comprised of traces and vias connected together for conductive transfer of a signal from the transmitter to the receiver; a parasitic element on the printed circuit board, the parasitic element having a parasitic effect that distorts the signal; and one or more passive elements mounted adjacent to the conductive pathway without connecting to the conductive pathway, the passive elements having a corrective effect to reduce the distortion from the parasitic effect on the signal.

Abstract translation: 公开了用于对抗信号失真的印刷电路板，其包括：在发射器和接收器之间的印刷电路板上的导电路径，由连接在一起的迹线和通孔组成的导电通路，用于将信号从发射器传导到接收器; 在印刷电路板上的寄生元件，寄生元件具有扭曲信号的寄生效应; 以及一个或多个无源元件安装在导电路径附近而不连接到导电路径，无源元件具有校正效果，以减少由信号引起的寄生效应的失真。

公开(公告)号：US20080301347A1

公开(公告)日：2008-12-04

申请号：US11756656

申请日：2007-06-01

Applicant: Justin P. Bandholz ,  Robert J. Christopher ,  Joseph M. Jacobs ,  Pravin Patel

Inventor： Justin P. Bandholz ,  Robert J. Christopher ,  Joseph M. Jacobs ,  Pravin Patel

IPC: G06F13/14 ,  H04H7/00

CPC classification number: G06F13/4072

Abstract: A system for allowing a designer to implement Universal Serial Bus (USB) 2.0 in topologies not anticipated by a USB 2.0 specification and with reduced channel losses, the system comprising: a bus channel having a plurality of electrical elements; and a boost circuit connected at a predetermined location on the bus channel; a plurality of USB signals transmitted through the system; wherein edges of the plurality of USB signals are boosted without impacting the bi-directional nature of the bus channel.

Abstract translation: 一种用于允许设计者在USB 2.0规范未预期的拓扑中实现通用串行总线（USB）2.0和减少的信道损失的系统，该系统包括：具有多个电气元件的总线通道; 以及连接在所述总线通道上的预定位置处的升压电路; 通过系统传输的多个USB信号; 其中所述多个USB信号的边缘被提升而不影响所述总线信道的双向性质。

公开(公告)号：US20140182667A1

公开(公告)日：2014-07-03

申请号：US13733362

申请日：2013-01-03

Applicant: Benjamin C. Richards ,  Yong Lin ,  Paul R. Sharps ,  Pravin Patel

Inventor： Benjamin C. Richards ,  Yong Lin ,  Paul R. Sharps ,  Pravin Patel

IPC: H01L31/0304 ,  H01L31/18 ,  H01L31/0725

CPC classification number: H01L31/18 ,  B82Y20/00 ,  H01L31/035236 ,  H01L31/0725 ,  H01L31/075 ,  H01L31/078 ,  H01L31/1852 ,  Y02E10/52 ,  Y02E10/544 ,  Y02E10/548 ,  Y02P70/521

Abstract: A multijunction photovoltaic cell including a top subcell; a second subcell disposed immediately adjacent to the top subcell and producing a first photo-generated current; and including a sequence of first and second different semiconductor layers with different lattice constant; and a lower subcell disposed immediately adjacent to the second subcell and producing a second photo-generated current substantially equal in amount to the first photo-generated current density.

Abstract translation: 一种包括顶部子电池的多结光伏电池; 第二子电池，其紧邻所述顶部子电池并且产生第一光生电流; 并且包括具有不同晶格常数的第一和第二不同半导体层的序列; 以及下部子电池，其紧邻所述第二子电池设置并且产生基本上等于所述第一光生电流密度的第二光生电流。

公开(公告)号：US08306652B2

公开(公告)日：2012-11-06

申请号：US12048624

申请日：2008-03-14

Applicant: Justin Potok Bandholz ,  Clifton Ehrich Kerr ,  Pravin Patel ,  Bruce James Wilkie

Inventor： Justin Potok Bandholz ,  Clifton Ehrich Kerr ,  Pravin Patel ,  Bruce James Wilkie

IPC: G06F15/173 ,  G06F15/16

CPC classification number: G06F13/4072 ,  H04L12/40032 ,  H05K7/1492

Abstract: In one embodiment, a communication system for a multi-blade server system includes a multi-drop serial bus network interconnecting a management module with each of a plurality of servers in a multi-server chassis. A first transceiver subsystem is configured for communicating over the serial bus network between the management module and each server within a first frequency band. A second transceiver subsystem is configured for simultaneously communicating over the serial bus network between the management module and the servers within a second frequency band higher than the first frequency band. A first signal-filtering subsystem substantially filters out signals in the second frequency band from the first transceiver subsystem. A second signal-filtering subsystem substantially filters out the signals in the first frequency band from the second transceiver subsystem.

Abstract translation: 在一个实施例中，用于多刀片服务器系统的通信系统包括将管理模块与多服务器机箱中的多个服务器中的每一个互连的多点串行总线网络。 第一收发器子系统被配置用于通过串行总线网络在管理模块和第一频带内的每个服务器之间进行通信。 第二收发器子系统被配置为在高于第一频带的第二频带内在管理模块和服务器之间通过串行总线网络同时通信。 第一信号滤波子系统基本上从第一收发器子系统滤出第二频带中的信号。 第二信号滤波子系统基本上从第二收发器子系统滤除第一频带中的信号。

公开(公告)号：US20120216083A1

公开(公告)日：2012-08-23

申请号：US13458319

申请日：2012-04-27

Applicant: David Windell ,  Pravin Patel ,  James Hughes ,  Christopher West ,  Robert Piper ,  Timothy Schlude

Inventor： David Windell ,  Pravin Patel ,  James Hughes ,  Christopher West ,  Robert Piper ,  Timothy Schlude

IPC: G06F11/07

CPC classification number: G06F11/325 ,  H04L41/0645

Abstract: Methods and systems for implementing such methods for providing server fault notifications, diagnostic and system management information may include, but are not limited to: receiving a network fault status request input; illuminating one or more server node fault indicators for one or more degraded server nodes having one or more faults; receiving a server node fault status request input for a degraded server node having one or more faults; and displaying one or more diagnostic service notifications for one or more faults of the degraded server node.The displaying of the diagnostic service notifications may allow for the completion of various service operations associated with the service notifications once the information specific to a fault is presented.

Abstract translation: 用于实现用于提供服务器故障通知，诊断和系统管理信息的这种方法的方法和系统可以包括但不限于：接收网络故障状态请求输入; 为具有一个或多个故障的一个或多个退化服务器节点照亮一个或多个服务器节点故障指示符; 接收具有一个或多个故障的劣化服务器节点的服务器节点故障状态请求输入; 以及显示针对所述退化服务器节点的一个或多个故障的一个或多个诊断服务通知。 一旦出现故障特有的信息，诊断服务通知的显示可以允许完成与服务通知相关联的各种服务操作。

公开(公告)号：US08199515B2

公开(公告)日：2012-06-12

申请号：US12644558

申请日：2009-12-22

Applicant: Justin P. Bandholz ,  Brian M. Kerrigan ,  Edward J. McNulty ,  Pravin Patel ,  Peter R. Seidel ,  Philip L. Weinstein

Inventor： Justin P. Bandholz ,  Brian M. Kerrigan ,  Edward J. McNulty ,  Pravin Patel ,  Peter R. Seidel ,  Philip L. Weinstein

IPC: H05K7/00

CPC classification number: G06F1/185 ,  Y10T29/49147

Abstract: A DIMM riser card that includes a PCB having a first edge, a second edge, and one or more faces. The first edge of the PCB is configured for insertion into a main board DIMM socket. The first edge includes electrical traces that electrically couple to a memory bus. The DIMM riser card includes an angled DIMM socket mounted on one face of the PCB, where the angled DIMM socket is configured to accept a DIMM at an angle not perpendicular to the PCB and electrically couple the DIMM to the memory bus. The DIMM riser card includes a straddle mount DIMM socket mounted on the second edge of the PCB. The straddle mount DIMM socket is configured to accept a DIMM and electrically couple the DIMM to the memory bus through the electrical traces on the first edge of the PCB.

Abstract translation: 一种DIMM转接卡，其包括具有第一边缘，第二边缘和一个或多个面部的PCB。 PCB的第一个边缘被配置为插入主板DIMM插槽。 第一个边缘包括电耦合到存储器总线的电迹线。 DIMM转接卡包括安装在PCB的一个面上的倾斜的DIMM插槽，其中倾斜的DIMM插槽被配置为以不垂直于PCB的角度接受DIMM并将DIMM电耦合到存储器总线。 DIMM转接卡包括安装在PCB第二边缘上的跨骑式DIMM插槽。 跨骑式DIMM插槽被配置为接受DIMM并通过PCB第一边缘上的电迹线将DIMM电连接到存储器总线。

公开(公告)号：US20110149499A1

公开(公告)日：2011-06-23

申请号：US12644558

申请日：2009-12-22

Applicant: Justin P. Bandholz ,  Brian M. Kerrigan ,  Edward J. McNulty ,  Pravin Patel ,  Peter R. Seidel ,  Philip L. Weinstein

Inventor： Justin P. Bandholz ,  Brian M. Kerrigan ,  Edward J. McNulty ,  Pravin Patel ,  Peter R. Seidel ,  Philip L. Weinstein

IPC: G06F1/16 ,  H05K7/00 ,  H01R9/00

CPC classification number: G06F1/185 ,  Y10T29/49147

Abstract: A DIMM riser card that includes a PCB having a first edge, a second edge, and one or more faces. The first edge of the PCB is configured for insertion into a main board DIMM socket. The first edge includes electrical traces that electrically couple to a memory bus. The DIMM riser card includes an angled DIMM socket mounted on one face of the PCB, where the angled DIMM socket is configured to accept a DIMM at an angle not perpendicular to the PCB and electrically couple the DIMM to the memory bus. The DIMM riser card includes a straddle mount DIMM socket mounted on the second edge of the PCB. The straddle mount DIMM socket is configured to accept a DIMM and electrically couple the DIMM to the memory bus through the electrical traces on the first edge of the PCB.

Abstract translation: 一种DIMM转接卡，其包括具有第一边缘，第二边缘和一个或多个面部的PCB。 PCB的第一个边缘被配置为插入主板DIMM插槽。 第一个边缘包括电耦合到存储器总线的电迹线。 DIMM转接卡包括安装在PCB的一个面上的倾斜的DIMM插槽，其中倾斜的DIMM插槽被配置为以不垂直于PCB的角度接受DIMM并将DIMM电耦合到存储器总线。 DIMM转接卡包括安装在PCB第二边缘上的跨骑式DIMM插槽。 跨骑式DIMM插槽被配置为接受DIMM并通过PCB第一边缘上的电迹线将DIMM电连接到存储器总线。

公开(公告)号：US07956688B2

公开(公告)日：2011-06-07

申请号：US12574923

申请日：2009-10-07

Applicant: Rubina F. Ahmed ,  Bradley D. Herrman ,  Pravin Patel ,  Peter R. Seidel

Inventor： Rubina F. Ahmed ,  Bradley D. Herrman ,  Pravin Patel ,  Peter R. Seidel

IPC: H03F3/45 ,  H03K19/094

CPC classification number: H04L25/0274 ,  H04L25/0284

Abstract: Embodiments of the invention include a common mode cancellation circuit and method for correcting signal skew in a differential circuit. According to one embodiment, an op amp circuit is used to correct the mismatch between transmission line lengths in the differential circuit. The CMCC can be embodied as an ASIC and added on to an existing differential signaling systems to correct and compensate for board wiring skew or other causes of phase misalignment. The result is restoration of the cross-over intersection of the plus and minus signals of the differential pair closer to the common voltage level point, as if the signals had been in phase.

Abstract translation: 本发明的实施例包括用于校正差分电路中的信号偏移的共模消除电路和方法。 根据一个实施例，使用运算放大器电路来校正差分电路中的传输线路长度之间的失配。 CMCC可以实现为ASIC，并添加到现有的差分信号系统上，以纠正和补偿电路板布线偏移或相位未对准的其他原因。 结果是恢复差分对的正负信号与公共电压电平点的交叉交叉，好像信号是同相的。

公开(公告)号：US20100231209A1

公开(公告)日：2010-09-16

申请号：US12402806

申请日：2009-03-12

Applicant: Rubina F. Ahmed ,  Moises Cases ,  Bradley D. Herrman ,  Bhyrav M. Mutnury ,  Pravin Patel ,  Peter R. Seidel

Inventor： Rubina F. Ahmed ,  Moises Cases ,  Bradley D. Herrman ,  Bhyrav M. Mutnury ,  Pravin Patel ,  Peter R. Seidel

IPC: G01R31/00

CPC classification number: G01R31/2806 ,  G01R15/183

Abstract: Testing an electrical component, the component including a printed circuit board (‘PCB’) with a number of traces, the traces organized in pairs with each trace of a pair carrying current in opposite directions and separated from one another by a substrate layer of the PCB, where testing of the electrical component includes: dynamically and iteratively until a present impedance for a pair of traces of the component is greater than a predetermined threshold impedance: increasing, by an impedance varying device at the behest of a testing device, magnetic field strength of a magnetic field applied to the pair of traces by the impedance varying device, including increasing the present impedance of the pair of traces; measuring, by the testing device, one or more operating parameters; and recording, by the testing device, the measurements of the operating parameters.

Abstract translation: 测试电气部件，该部件包括具有多个迹线的印刷电路板（“PCB”），该迹线与成对的每个迹线成对地沿着相反的方向承载电流，并且彼此分离由基底层 PCB，其中电气部件的测试包括：动态地和迭代地，直到组件的一对迹线的当前阻抗大于预定阈值阻抗：通过测试装置的阻抗改变装置增加磁场 通过阻抗变化装置施加到该对迹线的磁场的强度，包括增加该对迹线的当前阻抗; 由所述测试装置测量一个或多个操作参数; 并由测试装置记录操作参数的测量值。

公开(公告)号：US09646947B2

公开(公告)日：2017-05-09

申请号：US12644704

申请日：2009-12-22

Applicant: Justin P. Bandholz ,  Pravin Patel ,  Peter R. Seidel

Inventor： Justin P. Bandholz ,  Pravin Patel ,  Peter R. Seidel

IPC: H01L23/00 ,  H01L23/64 ,  H01L25/065 ,  H01L21/66 ,  H01L25/00

CPC classification number: H01L24/48 ,  H01L22/14 ,  H01L22/20 ,  H01L23/645 ,  H01L24/45 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/6611 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4809 ,  H01L2224/48092 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/85207 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/20751 ,  H01L2924/2076 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: An integrated circuit (IC) that includes a semiconductor die in an IC package. The semiconductor die includes an electrical endpoint. The IC also includes a pad affixed to the semiconductor die. The pad is characterized by a capacitance and is coupled to the electrical endpoint. The IC also includes a bond wire coupling the pad to an IC package pin. The bond wire is an inductor characterized by an inductance. The inductance is configured to decrease signal degradation caused by the capacitance of the pad on electrical signals transmitted between the pin and the electrical endpoint of the semiconductor die.