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公开(公告)号：US20170373025A1
公开(公告)日：2017-12-28
申请号：US15190158
申请日：2016-06-22
Applicant: QUALCOMM Incorporated
Inventor： Daeik Daniel KIM , Changhan Hobie YUN , David Francis BERDY , Chengjie ZUO , Mario Francisco VELEZ , Jonghae KIM
IPC: H01L23/64 , H01L23/522 , H01F41/04
CPC classification number: H01L23/645 , H01F41/041 , H01L23/49822 , H01L23/5227 , H01L23/5383 , H01L25/16 , H01L2224/16227 , H01L2924/19042 , H01L2924/19105 , H01L2924/30107
Abstract: In conventional device packages, separate standalone inductors are provided and mounted on an interposer substrate along with a die. Separate inductors reduce integration density, decrease flexibility, increase footprint, and generally increase costs. To address such disadvantages, it is proposed to provide a part of an inductor in a substrate below a die. The proposed stacked substrate inductor may include a first inductor in a first substrate, a second inductor in a second a second substrate stacked on the first substrate, and an inductor interconnect coupling the first and second inductors. The core regions of the first and second inductors may overlap with each other at least partially. The proposed stacked substrate inductor may enhance integration density, increase flexibility, decrease footprint, and/or reduce costs.
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公开(公告)号：US20160381809A1
公开(公告)日：2016-12-29
申请号：US15260249
申请日：2016-09-08
Applicant: QUALCOMM Incorporated
Inventor： Daeik Daniel KIM , Jonghae KIM , Chengjie ZUO , Changhan Hobie YUN , Mario Francisco VELEZ , Robert Paul MIKULKA
Abstract: Systems and methods relate to a semiconductor package comprising a first substrate or a 2D passive-on-glass (POG) structure with a passive component and a first set of one or more package pads formed on a face of a glass substrate. The semiconductor package also includes a second or laminate substrate with a second set of one or more package pads formed on a face of the second or laminate substrate. Solder balls are dropped, configured to contact the first set of one or more package pads with the second set of one or more package pads, wherein the first substrate or the 2D POG structure is placed face-up on the face of the second or laminate substrate. A printed circuit board (PCB) can be coupled to a bottom side of the second or laminate substrate.
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公开(公告)号：US20160254236A1
公开(公告)日：2016-09-01
申请号：US14633934
申请日：2015-02-27
Applicant: QUALCOMM Incorporated
Inventor： Daeik Daniel KIM , Changhan Hobie YUN , Mario Francisco VELEZ , David Francis BERDY , Chengjie ZUO , Jonghae KIM , Matthew Michael NOWAK
IPC: H01L23/60 , H01L25/00 , H01L23/00 , H01L25/065 , H01L23/31
CPC classification number: H01L23/60 , H01L23/3114 , H01L23/552 , H01L24/00 , H01L24/17 , H01L25/0655 , H01L25/50 , H01L2224/16235 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125
Abstract: Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a multichip module or device, such as a multichip module or device with flip-chip (FC) bumps. Intra-module shielding between individual chips within the multichip module or device is achieved by electromagnetic or radio-signal (RF) isolation provided by the surfaces of the conductor shield immediately surrounding each of the chips. The conductor shield is directly connected to one or more grounded conductor portions of a substrate or interposer to ensure reliable grounding.
Abstract translation: 接地屏蔽通过具有导电表面的导体屏蔽来实现，导电表面立即围绕多芯片模块或器件（例如具有倒装芯片（FC）凸块的多芯片模块或器件）中的单个芯片。 多芯片模块或设备内的单个芯片之间的模块间屏蔽通过由紧邻每个芯片的导体屏蔽表面提供的电磁或射频信号（RF）隔离来实现。 导体屏蔽件直接连接到基板或插入件的一个或多个接地导体部分，以确保可靠的接地。
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公开(公告)号：US20150200049A1
公开(公告)日：2015-07-16
申请号：US14155172
申请日：2014-01-14
Applicant: Qualcomm Incorporated
Inventor： Daeik Daniel KIM , Jonghae KIM , Chengjie ZUO , Mario Francisco VELEZ , Changhan Hobie YUN
CPC classification number: H01F41/041 , H01F27/2804 , H01F41/00 , H01F2017/0086 , H01F2027/2809 , H01L2924/0002 , Y10T29/4902 , H01L2924/00
Abstract: A 3D nested transformer includes a substrate having a set of through substrate vias daisy chained together with a set of traces. At least some of the through substrate vias have first and second conductive regions. The set of traces also includes a first set of traces coupling together at least some of the first conductive regions of the through substrate vias, and a second set of traces coupling together at least some of the second conductive regions of the through substrate vias.
Abstract translation: 3D嵌套变压器包括具有与一组迹线菊花链连接的一组通过衬底通孔的衬底。 至少一些直通衬底通孔具有第一和第二导电区域。 该组迹线还包括将至少一些贯穿衬底通孔的第一导电区域耦合在一起的第一组迹线，以及将至少一些第二导电区域连接在一起的穿过衬底通孔的第二组迹线。
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15.发明申请公开(公告)号：US20150070863A1
公开(公告)日：2015-03-12
申请号：US14020558
申请日：2013-09-06
Applicant: QUALCOMM Incorporated
Inventor： Changhan Hobie YUN , Chengjie ZUO , Jonghae KIM , Daeik Daniel KIM , Mario Francisco VELEZ
CPC classification number: H05K1/162 , H01L23/49822 , H01L23/50 , H01L2224/16225 , H01L2924/15311 , H05K1/0306 , H05K1/032 , H05K1/115 , H05K1/181 , H05K3/46 , H05K2201/10378 , H05K2201/10674 , Y10T29/49165
Abstract: An interposer for a chipset includes multilayer thin film capacitors incorporated therein to reduce parasitic inductance in the chipset. Power and ground terminals are laid out in a staggered pattern to cancel magnetic fields between conductive vias to reduce equivalent series inductance (ESL).
Abstract translation: 用于芯片组的插入件包括并入其中的多层薄膜电容器，以减少芯片组中的寄生电感。 电源和接地端子布置成交错图案，以消除导电通孔之间的磁场，以减少等效串联电感（ESL）。
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Patent Agency Ranking
公开(公告)号：US20180083589A1
公开(公告)日：2018-03-22
申请号：US15273596
申请日：2016-09-22
Applicant: QUALCOMM Incorporated
Inventor： Changhan Hobie YUN , Chengjie ZUO , David Francis BERDY , Mario Francisco VELEZ , Niranjan Sunil MUDAKATTE , Jonghae KIM
CPC classification number: H03H7/0115 , H03H7/463 , H03H2001/0078 , H03H2001/0085 , H03H2007/013
Abstract: The present disclosure provides circuits and methods for fabricating circuits. A circuit may include a first insulator, a second insulator, a first subset of circuit elements disposed on a bottom surface of the first insulator, a second subset of circuit elements disposed on a top surface of the second insulator, one or more conductive couplings disposed between the first subset of circuit elements and the second subset of circuit elements.
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公开(公告)号：US20180083588A1
公开(公告)日：2018-03-22
申请号：US15350969
申请日：2016-11-14
Applicant: QUALCOMM Incorporated
Inventor： Changhan Hobie YUN , Shiqun GU , Je-Hsiung Jeffrey LAN , Jonghae KIM , Niranjan Sunil MUDAKATTE , David Francis BERDY , Mario Francisco VELEZ , Chengjie ZUO
CPC classification number: H03H1/00 , H01G4/005 , H01G4/012 , H01G4/1209 , H01G4/33 , H01G4/40 , H01L23/5223 , H01L28/60 , H03H7/46 , H03H7/463 , H03H2001/0014 , H03H2001/0021 , H04B1/0057 , H04B1/0458 , H04B1/18
Abstract: A capacitor may include a first capacitor plate having a first length. The capacitor may also include an inorganic capacitor dielectric layer on sidewalls and a surface of the first capacitor plate and a second capacitor plate on the inorganic capacitor dielectric layer. The second capacitor plate may have a second length less than the first length of the first capacitor plate. The capacitor may also include a conductive contact landing directly on the first capacitor plate. The conductive contact may land directly on the first capacitor plate by extending through the inorganic capacitor dielectric layer and an organic interlayer dielectric supported by the inorganic capacitor dielectric layer.
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公开(公告)号：US20170338255A1
公开(公告)日：2017-11-23
申请号：US15161152
申请日：2016-05-20
Applicant: QUALCOMM Incorporated
Inventor： Changhan Hobie YUN , Daeik Daniel KIM , Jonghae KIM , Mario Mario VELEZ , Chengjie ZUO , David Francis BERDY
CPC classification number: H01L27/13 , H01L21/84 , H01L23/49822 , H01L28/10 , H01L28/40 , H03H7/0115 , H03H2001/0085
Abstract: The present disclosure provides integrated circuit apparatuses and methods for manufacturing integrated circuit apparatuses. An integrated circuit apparatus may include a first insulator, the first insulator being substantially planar and having a first top surface and a first bottom surface opposite the first top surface, a first conductor disposed on the first insulator, a second insulator, the second insulator being substantially planar and having a second top surface and a second bottom surface opposite the second top surface, a second conductor disposed on the second insulator, and a dielectric layer disposed between the first bottom conductor of the first insulator and the second top conductor of the second insulator.
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19.发明申请公开(公告)号：US20170140862A1
公开(公告)日：2017-05-18
申请号：US14941493
申请日：2015-11-13
Applicant: QUALCOMM Incorporated
Inventor： Changhan Hobie YUN , David Francis BERDY , Daeik Daniel KIM , Chengjie ZUO , Jonghae KIM , Je-Hsiung Jeffrey LAN , Mario Francisco VELEZ , Niranjan Sunil MUDAKATTE
CPC classification number: H01F10/12 , H01F17/0013 , H01F27/2804 , H01F41/042 , H01F41/046 , H01F2017/0066 , H01F2027/2809
Abstract: A thin film magnet (TFM) three-dimensional (3D) inductor structure may include a substrate with conductive vias extending through the substrate. The TFM 3D inductor structure may also include a magnetic thin film layer on at least sidewalls of the conductive vias and on a first side and an opposing second side of the substrate. The TFM 3D inductor structure may further include a first conductive trace directly on the magnetic thin film layer on the first side of the substrate and electrically coupling to at least one of the conductive vias. The TFM 3D inductor structure also includes a second conductive trace directly on the magnetic thin film layer on the second side of the substrate and coupled to at least one of the conductive vias.
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公开(公告)号：US20170110237A1
公开(公告)日：2017-04-20
申请号：US15191203
申请日：2016-06-23
Applicant: QUALCOMM Incorporated
Inventor： Daeik Daniel KIM , Mario Francisco VELEZ , Changhan Hobie YUN , Niranjan Sunil MUDAKATTE , Jonghae KIM , Chengjie ZUO , David Francis BERDY
CPC classification number: H01F27/2847 , H01F17/0013 , H01F41/04 , H01F41/041 , H01F2017/002 , H01F2017/004 , H03F15/00 , H03H7/0138
Abstract: Disclosed is an inductor device including a first curved metal plate, a second curved metal plate below and substantially vertically aligned with the first curved metal plate, and a first elongated via vertically aligned between the first curved metal plate and the second curved metal plate, the first elongated via configured to conductively couple the first curved metal plate to the second curved metal plate and having an aspect ratio of a width to a height of the first elongated via of at least approximately 2 to 1.
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