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    Electrostatic protection for stacked multi-chip integrated circuits
    11.
    发明授权
    Electrostatic protection for stacked multi-chip integrated circuits 有权
    堆叠多芯片集成电路的静电保护

    公开(公告)号：US09184130B2

    公开(公告)日：2015-11-10

    申请号：US13646109

    申请日：2012-10-05

    Applicant: QUALCOMM Incorporated

    Inventor： Brian M. Henderson ,  Chiew-Guan Tan ,  Gregory A. Uvieghara ,  Reza Jalilizeinali

    IPC: H02H9/00 ,  H01L23/525 ,  H01L23/60 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/48

    CPC classification number: H01L23/5256 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/60 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/73257 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014

    Abstract: One feature pertains to a multi-chip module that comprises at least a first integrated circuit (IC) die and a second IC die. The second IC die has an input/output (I/O) node electrically coupled to the first IC die by a through substrate via. The second die's active surface also includes a fuse that is electrically coupled to the I/O node and adapted to protect the second IC die from damage caused by an electrostatic discharge (ESD). In particular, the fuse protects the second IC die from ESD that may be generated as a result of electrically coupling the first die to the second die during the manufacturing of the multi-chip module. Upon coupling the first die to the second die, the fuse may bypass the ESD current generated by the ESD to ground. After packaging of the multi-chip module is complete, the fuse may be blown open.

    Abstract translation: 一个特征涉及包括至少第一集成电路（IC）管芯和第二IC管芯的多芯片模块。 第二IC芯片具有通过基板通孔电耦合到第一IC裸片的输入/输出（I / O）节点。 第二管芯的有源表面还包括电连接到I / O节点并且适于保护第二IC管芯免受静电放电（ESD）引起的损坏的熔丝。 特别地，保险丝保护第二IC芯片免受由于在多芯片模块的制造期间将第一裸片电耦合到第二裸片而产生的ESD。 在将第一管芯耦合到第二管芯时，熔丝可以将由ESD产生的ESD电流旁路到地。 多芯片模块封装完成后，保险丝可能会断开。

    OUTPUT DRIVER WITH BACK-POWERING PREVENTION
    16.
    发明申请
    OUTPUT DRIVER WITH BACK-POWERING PREVENTION 有权
    输出驱动器与备用电源预防

    公开(公告)号：US20160248418A1

    公开(公告)日：2016-08-25

    申请号：US14631347

    申请日：2015-02-25

    Applicant: QUALCOMM Incorporated

    Inventor： Wilson Jianbo Chen ,  Chiew-Guan Tan ,  Reza Jalilizeinali

    IPC: H03K17/26 ,  H03K17/18

    CPC classification number: H03K17/26 ,  H03K17/18 ,  H03K19/00315 ,  H03K19/00361

    Abstract: A back-power prevention circuit is provided that protects a buffer transistor from back-power during a back-power condition by charging a signal lead coupled to a gate of the buffer transistor to a pad voltage and by charging a body of the buffer transistor to the pad voltage.

    Abstract translation: 提供了一种后置功率防止电路，其通过将耦合到缓冲晶体管的栅极的信号引线充电到焊盘电压并且通过将缓冲晶体管的主体充电到基板来保护缓冲晶体管免受后功率状态下的反向功率 焊盘电压。

    ELECTROSTATIC PROTECTION FOR STACKED MULTI-CHIP INTEGRATED CIRCUITS
    18.
    发明申请
    ELECTROSTATIC PROTECTION FOR STACKED MULTI-CHIP INTEGRATED CIRCUITS 有权
    用于堆叠多芯片集成电路的静电保护

    公开(公告)号：US20140098448A1

    公开(公告)日：2014-04-10

    申请号：US13646109

    申请日：2012-10-05

    Applicant: QUALCOMM INCORPORATED

    Inventor： Brian M. Henderson ,  Chiew-Guan Tan ,  Gregory A. Uvieghara ,  Reza Jalilizeinali

    IPC: H02H9/04 ,  H01L21/44

    CPC classification number: H01L23/5256 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/60 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/73257 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014

    Abstract: One feature pertains to a multi-chip module that comprises at least a first integrated circuit (IC) die and a second IC die. The second IC die has an input/output (I/O) node electrically coupled to the first IC die by a through substrate via. The second die's active surface also includes a fuse that is electrically coupled to the I/O node and adapted to protect the second IC die from damage caused by an electrostatic discharge (ESD). In particular, the fuse protects the second IC die from ESD that may be generated as a result of electrically coupling the first die to the second die during the manufacturing of the multi-chip module. Upon coupling the first die to the second die, the fuse may bypass the ESD current generated by the ESD to ground. After packaging of the multi-chip module is complete, the fuse may be blown open.

    Abstract translation: 一个特征涉及包括至少第一集成电路（IC）管芯和第二IC管芯的多芯片模块。 第二IC芯片具有通过基板通孔电耦合到第一IC裸片的输入/输出（I / O）节点。 第二管芯的有源表面还包括电连接到I / O节点并且适于保护第二IC管芯免受静电放电（ESD）引起的损坏的熔丝。 特别地，保险丝保护第二IC芯片免受由于在多芯片模块的制造期间将第一裸片电耦合到第二裸片而产生的ESD。 在将第一管芯耦合到第二管芯时，熔丝可以将由ESD产生的ESD电流旁路到地。 多芯片模块封装完成后，保险丝可能会断开。

    Dynamic gate-overdrive voltage boost receiver
    19.
    发明授权
    Dynamic gate-overdrive voltage boost receiver 有权

    公开(公告)号：US11637356B1

    公开(公告)日：2023-04-25

    申请号：US17649526

    申请日：2022-01-31

    Applicant: QUALCOMM Incorporated

    Inventor： Aliasgar Presswala ,  Wilson Jianbo Chen ,  Chiew-Guan Tan

    IPC: H03K19/0185 ,  H01P5/12 ,  H02M3/155

    Abstract: In certain aspects, a receiving circuit includes a splitter, a first receiver, a second receiver, and a boost circuit. The splitter is configured to receive an input signal, split the input signal into a first signal and a second signal, output the first signal to the first receiver, and output the second signal to the second receiver. In certain aspects, the voltage swing of the input signal is split between the first signal and the second signal. The boost circuit may be configured to shift a supply voltage of the second receiver to boost a gate-overdrive voltage of a transistor in the second receiver during a transition of the input signal (e.g., transition from low to high). In certain aspects, the boost circuit controls the gate-overdrive voltage boosting based on the first signal and the second signal.

    Level shifter with auto voltage-bias reliability protection
    20.
    发明授权
    Level shifter with auto voltage-bias reliability protection 有权

    公开(公告)号：US10911047B1

    公开(公告)日：2021-02-02

    申请号：US16743617

    申请日：2020-01-15

    Applicant: QUALCOMM Incorporated

    Inventor： Rohit Shetty ,  Chiew-Guan Tan ,  Gregory Lynch

    IPC: H03K19/003 ,  H03K19/00 ,  H03K3/356 ,  H03K3/012 ,  H03K19/0185

    Abstract: Certain aspects of the present disclosure generally relate to a level-shifting circuit. The level-shifting circuit generally includes a first pull-up path having at least one first diode and at least one first transistor, and a second pull-up path having at least one second diode and at least one second transistor. The level-shifting circuit may also include a first pull-down path having a third transistor and a fourth transistor, wherein the fourth transistor is coupled between the third transistor and the first diode; a second pull-down path having a fifth transistor and a sixth transistor, wherein the sixth transistor is coupled between the fifth transistor and the second diode; and an overvoltage protection circuit coupled to gates of the fourth transistor and the sixth transistor.

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