公开(公告)号：US09148979B2

公开(公告)日：2015-09-29

申请号：US13706492

申请日：2012-12-06

Applicant: QUALCOMM Incorporated

Inventor： Victor A. Chiriac ,  Dexter T. Chun

IPC: H05K7/20 ,  G06F1/20 ,  H05K13/04 ,  H01L23/473

CPC classification number: H05K7/20436 ,  G06F1/203 ,  G06F1/206 ,  G06F2200/203 ,  H05K13/04 ,  Y10T29/49117

Abstract: Some implementations provide a folding electronic device that includes a base portion, a cover portion and a coupler. The base portion includes a region configured to generate heat. The cover portion includes a display screen, a heat dissipating component, and a thermally insulating component. The heat dissipating component is coplanar to the display screen. The thermally insulating component is coplanar to the display screen. The thermally insulating component is located between the display screen and the heat dissipating component. The coupler is for thermally coupling the base portion to the cover portion. The coupler includes a first component and a second component. The first component is coupled to the region configured to generate heat. The second component is coupled to the heat dissipating component of the cover portion. The coupler provides a path for transferring heat.

Abstract translation: 一些实施方案提供一种折叠电子设备，其包括基部，盖部分和耦合器。 基部包括被配置为产生热量的区域。 盖部分包括显示屏，散热部件和隔热部件。 散热部件与显示屏共面。 隔热部件与显示屏共面。 隔热部件位于显示屏和散热部件之间。 联接器用于将基部热耦合到盖部分。 耦合器包括第一部件和第二部件。 第一部件耦合到被配置为产生热量的区域。 第二部件耦合到盖部分的散热部件。 耦合器提供传递热量的路径。

公开(公告)号：US09092327B2

公开(公告)日：2015-07-28

申请号：US13781366

申请日：2013-02-28

Applicant: QUALCOMM Incorporated

Inventor： Subrato K. De ,  Richard A. Stewart ,  Gheorghe Calin Cascaval ,  Dexter T. Chun

IPC: G06F12/00 ,  G11C7/00 ,  G06F12/06 ,  G11C7/10

CPC classification number: G06F12/023 ,  G06F12/0607 ,  G06F12/0638 ,  G06F2212/1044 ,  G11C7/1072 ,  Y02D10/13

Abstract: Systems and methods are provided for allocating memory to dissimilar memory devices. An exemplary embodiment includes a method for allocating memory to dissimilar memory devices. An interleave bandwidth ratio is determined, which comprises a ratio of bandwidths for two or more dissimilar memory devices. The dissimilar memory devices are interleaved according to the interleave bandwidth ratio to define two or more memory zones having different performance levels. Memory address requests are allocated to the memory zones based on a quality of service (QoS).

Abstract translation: 提供了系统和方法，用于将存储器分配给不同的存储器件。 示例性实施例包括用于将不同的存储器件分配存储器的方法。 确定交织带宽比，其包括两个或多个不同存储器件的带宽比。 不同的存储器件根据交织带宽比进行交织以定义具有不同性能级别的两个或多个存储器区域。 基于服务质量（QoS）将内存地址请求分配给内存区域。

公开(公告)号：US09088445B2

公开(公告)日：2015-07-21

申请号：US13787926

申请日：2013-03-07

Applicant: QUALCOMM Incorporated

Inventor： Dexter T. Chun ,  Sumeet S. Sethi ,  John D. Eaton ,  Vinodh R. Cuppu ,  Vikram Arora ,  Vaishnav Srinivas ,  Asim Muhammad Muneer ,  Isaac D. Berk

IPC: H03K17/16 ,  H04L25/02 ,  G06F13/40 ,  H03K19/00

CPC classification number: H04L25/0278 ,  G06F13/4086 ,  H03K19/0005 ,  H03K19/017545 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method of controlling signal termination includes providing first logic for selectively terminating signals received at a first device on a bidirectional data bus, providing second logic for selectively terminating signals received at a second device on the bidirectional data bus, sending first signals from the first device to the second device on the bidirectional data bus at a first speed, stopping the sending of the first signals, after stopping the sending of the first signals, enabling the second logic and shifting a reference voltage of the second device from a first level to a second level, after enabling the second logic at the second device, sending second signals from the first device to the second device on the bidirectional data bus at a higher speed, and controlling the first logic based on a speed of signals received at the first device on the bidirectional data bus.

Abstract translation: 一种控制信号终止的方法包括：提供用于选择性地终止在双向数据总线上在第一设备处接收的信号的第一逻辑，提供用于选择性地终止在双向数据总线上的第二设备处接收的信号的第二逻辑，从第一设备发送第一信号 以第一速度传送到双向数据总线上的第二设备，在停止发送第一信号之后停止发送第一信号，使得第二逻辑能够使第二设备的参考电压从第一电平移位到 在第二设备启用第二逻辑之后，以更高的速度在双向数据总线上从第一设备向第二设备发送第二信号，并且基于在第一设备处接收到的信号的速度来控制第一逻辑 在双向数据总线上。

公开(公告)号：US20140164720A1

公开(公告)日：2014-06-12

申请号：US13781320

申请日：2013-02-28

Applicant: QUALCOMM INCORPORATED

Inventor： Richard A. Stewart ,  Dexter T. Chun

IPC: G06F12/06

CPC classification number: G06F12/0607 ,  G06F13/1647

Abstract: Systems and methods are provided for dynamically allocating a memory subsystem. An exemplary embodiment comprises a method for dynamically allocating a memory subsystem in a portable computing device. The method involves fully interleaving a first portion of a memory subsystem having memory components with asymmetric memory capacities. A second remaining portion of the memory subsystem is partial interleaved according to an interleave bandwidth ratio. The first portion of the memory subsystem is allocated to one or more high-performance memory clients. The second remaining portion is allocated to one or more relatively lower-performance memory clients.

Abstract translation: 提供了用于动态分配存储器子系统的系统和方法。 示例性实施例包括用于在便携式计算设备中动态分配存储器子系统的方法。 该方法涉及完全交织具有具有非对称存储器容量的存储器组件的存储器子系统的第一部分。 存储器子系统的第二剩余部分根据交织带宽比被部分交织。 内存子系统的第一部分被分配给一个或多个高性能内存客户端。 第二剩余部分被分配给一个或多个相对较低性能的存储器客户端。

公开(公告)号：US20140164689A1

公开(公告)日：2014-06-12

申请号：US13726537

申请日：2012-12-24

Applicant: QUALCOMM INCORPORATED

Inventor： Dexter T. Chun ,  Serag Gadelrab ,  Stephen Molloy ,  Thomas Zeng

IPC: G06F12/06

CPC classification number: G06F12/0607 ,  G06F13/1647 ,  G06F13/1694

Abstract: Systems and methods are provided for managing performance of a computing device having dissimilar memory types. An exemplary embodiment comprises a method for interleaving dissimilar memory devices. The method involves determining an interleave bandwidth ratio comprising a ratio of bandwidths for two or more dissimilar memory devices. The dissimilar memory devices are interleaved according to the interleave bandwidth ratio. Memory address requests are distributed from one or more processing units to the dissimilar memory devices according to the interleave bandwidth ratio.

Abstract translation: 提供了用于管理具有不同存储器类型的计算设备的性能的系统和方法。 示例性实施例包括用于交错不同存储器件的方法。 该方法涉及确定包括两个或多个不同存储器件的带宽比的交织带宽比。 不同的存储器件根据交织带宽比进行交织。 存储器地址请求根据交织带宽比从一个或多个处理单元分配到不同的存储器设备。

公开(公告)号：US20140098489A1

公开(公告)日：2014-04-10

申请号：US13706492

申请日：2012-12-06

Applicant: QUALCOMM INCORPORATED

Inventor： Victor A. Chiriac ,  Dexter T. Chun

IPC: H05K7/20 ,  H05K13/04 ,  G06F1/20

CPC classification number: H05K7/20436 ,  G06F1/203 ,  G06F1/206 ,  G06F2200/203 ,  H05K13/04 ,  Y10T29/49117

Abstract: Some implementations provide a folding electronic device that includes a base portion, a cover portion and a coupler. The base portion includes a region configured to generate heat. The cover portion includes a display screen, a heat dissipating component, and a thermally insulating component. The heat dissipating component is coplanar to the display screen. The thermally insulating component is coplanar to the display screen. The thermally insulating component is located between the display screen and the heat dissipating component. The coupler is for thermally coupling the base portion to the cover portion. The coupler includes a first component and a second component. The first component is coupled to the region configured to generate heat. The second component is coupled to the heat dissipating component of the cover portion. The coupler provides a path for transferring heat.

Abstract translation: 一些实施方案提供一种折叠电子设备，其包括基部，盖部分和耦合器。 基部包括被配置为产生热量的区域。 盖部分包括显示屏，散热部件和隔热部件。 散热部件与显示屏共面。 隔热部件与显示屏共面。 隔热部件位于显示屏和散热部件之间。 联接器用于将基部热耦合到盖部分。 耦合器包括第一部件和第二部件。 第一部件耦合到被配置为产生热量的区域。 第二部件耦合到盖部分的散热部件。 耦合器提供传递热量的路径。

公开(公告)号：US09575884B2

公开(公告)日：2017-02-21

申请号：US13892433

申请日：2013-05-13

Applicant: QUALCOMM Incorporated

Inventor： Dexter T. Chun ,  Anand Srinivasan ,  Hyunsuk Shin ,  Steven Haehnichen

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7203

Abstract: Aspects include systems and methods for increasing performance of a flash translation layer (FTL) of a flash memory device. A copy of FTL tables stored on a flash memory device may be copied to a memory of a host device. The copy of the FTL tables may be directly accessed by the flash memory device to translate between logical addresses provided by the host device for read/write operations from/to a flash memory of the flash memory device, and the respective physical addresses of the flash memory. The flash memory device is granted direct memory access to a portion of the memory of the host device where the copy of the FTL tables is stored. The flash memory device bus masters communication busses connecting the flash memory device to the memory of the host device.

Abstract translation: 方面包括用于增加闪存设备的闪存转换层（FTL）的性能的系统和方法。 存储在闪存设备上的FTL表的副本可以被复制到主机设备的存储器。 FTL表的副本可以由闪存设备直接访问，以在主机设备提供的逻辑地址之间转换用于从闪存设备的闪速存储器读取/写入操作的闪存以及闪存的相应物理地址 记忆。 闪存设备被授予对存储FTL表的副本的主机设备的存储器的一部分的直接存储器访问。 闪存设备总线将连接闪存设备的通信总线连接到主机设备的存储器。

公开(公告)号：US09177623B2

公开(公告)日：2015-11-03

申请号：US13842515

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Shree Krishna Pandey ,  Dexter T. Chun

IPC: G06F1/10 ,  G11C7/22 ,  G06F13/16 ,  G06F13/42

CPC classification number: G11C7/227 ,  G06F1/10 ,  G06F13/1689 ,  G06F13/4243

Abstract: A memory interface includes circuitry configured for applying a variable delay to a portion of a data signal and applying a variable delay to a data strobe. The delayed data strobe samples the delayed portion of the data signal. Delayed portions of the data signal are spaced away from non-delayed portions of the data signal by alternating the routing of delayed bits and non-delayed bits of the data signal. A training block determines and sets a value of the variable delay corresponding to a largest value of a number of recorded eye aperture widths.

Abstract translation: 存储器接口包括经配置以将可变延迟应用于数据信号的一部分并将可变延迟应用于数据选通的电路。 延迟数据选通对数据信号的延迟部分进行采样。 通过交替数据信号的延迟位和非延迟位的路由，数据信号的延迟部分与数据信号的非延迟部分间隔开。 训练块确定并设置与记录的眼孔宽度的数量的最大值相对应的可变延迟的值。

公开(公告)号：US08959298B2

公开(公告)日：2015-02-17

申请号：US13726537

申请日：2012-12-24

Applicant: QUALCOMM Incorporated

Inventor： Dexter T. Chun ,  Serag Gadelrab ,  Stephen Molloy ,  Thomas Zeng

IPC: G06F12/00 ,  G06F12/06 ,  G06F13/16

CPC classification number: G06F12/0607 ,  G06F13/1647 ,  G06F13/1694

Abstract: Systems and methods are provided for managing performance of a computing device having dissimilar memory types. An exemplary embodiment comprises a method for interleaving dissimilar memory devices. The method involves determining an interleave bandwidth ratio comprising a ratio of bandwidths for two or more dissimilar memory devices. The dissimilar memory devices are interleaved according to the interleave bandwidth ratio. Memory address requests are distributed from one or more processing units to the dissimilar memory devices according to the interleave bandwidth ratio.

Abstract translation: 提供了用于管理具有不同存储器类型的计算设备的性能的系统和方法。 示例性实施例包括用于交错不同存储器件的方法。 该方法涉及确定包括两个或多个不同存储器件的带宽比的交织带宽比。 不同的存储器件根据交织带宽比进行交织。 存储器地址请求根据交织带宽比从一个或多个处理单元分配到不同的存储器设备。

公开(公告)号：US20140337560A1

公开(公告)日：2014-11-13

申请号：US13892433

申请日：2013-05-13

Applicant: QUALCOMM Incorporated

Inventor： Dexter T. Chun ,  Anand Srinivasan ,  Hyunsuk Shin ,  Steve Haehnichen

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7203

Abstract: Aspects include systems and methods for increasing performance of a flash translation layer (FTL) of a flash memory device. A copy of FTL tables stored on a flash memory device may be copied to a memory of a host device. The copy of the FTL tables may be directly accessed by the flash memory device to translate between logical addresses provided by the host device for read/write operations from/to a flash memory of the flash memory device, and the respective physical addresses of the flash memory. The flash memory device is granted direct memory access to a portion of the memory of the host device where the copy of the FTL tables is stored. The flash memory device bus masters communication busses connecting the flash memory device to the memory of the host device.

Abstract translation: 方面包括用于增加闪存设备的闪存转换层（FTL）的性能的系统和方法。 存储在闪存设备上的FTL表的副本可以被复制到主机设备的存储器。 FTL表的副本可以由闪存设备直接访问，以在主机设备提供的逻辑地址之间转换用于从闪存设备的闪速存储器读取/写入操作的闪存以及闪存的相应物理地址 记忆。 闪存设备被授予对存储FTL表的副本的主机设备的存储器的一部分的直接存储器访问。 闪存设备总线将连接闪存设备的通信总线连接到主机设备的存储器。