公开(公告)号：US20140354338A1

公开(公告)日：2014-12-04

申请号：US13905052

申请日：2013-05-29

Applicant: QUALCOMM Incorporated

Inventor： Kashyap Ramachandra Bellur ,  HariKrishna Chintarlapalli Reddy ,  Martin Saint-Laurent ,  Pratyush Kamal ,  Prayag Bhanubhai Patel ,  Esin Terzioglu

IPC: H03K3/037 ,  G06F17/50

CPC classification number: H03K3/037 ,  G06F17/5068 ,  G06F17/5081 ,  H03K3/012 ,  H03K3/356

Abstract: A circuit includes a pulsed-latch circuit. The pulsed-latch circuit includes a first plurality of transistors. One or more of the first plurality of transistors is length-of-diffusion (LOD) protected.

Abstract translation: 电路包括脉冲锁存电路。 脉冲锁存电路包括第一多个晶体管。 第一多个晶体管中的一个或多个是扩散长度（LOD）保护的。

公开(公告)号：US20140266398A1

公开(公告)日：2014-09-18

申请号：US13799686

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Chulmin Jung ,  Sei Seung Yoon ,  Esin Terzioglu ,  Hari Ananthanarayanan ,  Venugopal Boynapalli

IPC: H03K17/00

CPC classification number: H03K17/002 ,  G11C7/02 ,  G11C7/10 ,  G11C7/1006

Abstract: A semiconductor apparatus is provided herein for reducing power when transmitting data between a first device and a second device in the semiconductor apparatus. Additional circuitry is added to the semiconductor apparatus to create a communication system that decreases a number of state changes for each signal line of a data bus between the first device and the second device for all communications. The additional circuitry includes a decoder coupled to receive and convert a value from the first device for transmission over the data bus to an encoder that provides a recovered (i.e., re-encoded) version of the value to the second device. One or more multiplexers may also be included in the additional circuitry to support any number of devices.

Abstract translation: 本发明提供一种半导体装置，用于在半导体装置中的第一装置和第二装置之间传输数据时降低功率。 向半导体装置添加附加电路以创建通信系统，该通信系统减少用于所有通信的第一设备和第二设备之间的数据总线的每个信号线的状态变化的数量。 附加电路包括解码器，其耦合以接收和转换来自第一设备的值，用于通过数据总线传输到向第二设备提供值的恢复（即重新编码）版本的编码器。 一个或多个多路复用器也可以包括在附加电路中以支持任何数量的设备。

公开(公告)号：US08787096B1

公开(公告)日：2014-07-22

申请号：US13742964

申请日：2013-01-16

Applicant: QUALCOMM Incorporated

Inventor： Esin Terzioglu ,  Gregory Ameriada Uvieghara ,  Sei Seung Yoon ,  Balachander Ganesan ,  Anil Chowdary Kota

IPC: G11C7/00 ,  G11C13/00

CPC classification number: H03K17/223 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C13/0069 ,  G11C17/18 ,  H03K17/08104 ,  H03K17/6872 ,  H03K19/00315 ,  H03K2217/0018 ,  H03K2217/0063 ,  H03K2217/0072

Abstract: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.

Abstract translation: 公开了一种双模式PMOS晶体管，其具有第一工作模式，其中用于双模式PMOS晶体管的开关n阱被偏置到高电压。 双模式PMOS晶体管具有第二工作模式，其中开关n阱被偏置成低于高电压的低电压。 双模式PMOS晶体管的尺寸和栅极氧化物厚度各自具有不能适应与高电压的永久连接的幅度。 n阱电压开关电路偏置开关n阱，以防止电压损坏双模PMOS晶体管，尽管其尺寸相对较小，栅极氧化物厚度较薄。

公开(公告)号：US20140185348A1

公开(公告)日：2014-07-03

申请号：US13730487

申请日：2012-12-28

Applicant: QUALCOMM INCORPORATED

Inventor： Rakesh Vattikonda ,  Nishith Desai ,  ChangHo Jung ,  Sei Seung Yoon ,  Esin Terzioglu

IPC: G11C15/00

CPC classification number: G11C15/00 ,  G11C15/04

Abstract: A method within a hybrid ternary content addressable memory (TCAM) includes comparing a first portion of a search word to a first portion of a stored word in a first TCAM stage. The method further includes interfacing an output of the first TCAM stage to an input of the second TCAM stage. The method also includes comparing a second portion of the search word to a second portion of the stored word in a second TCAM stage when the first portion of the search word matches the first portion of the stored word. The first TCAM stage is different from the second TCAM stage.

Abstract translation: 混合三元内容可寻址存储器（TCAM）内的方法包括将搜索词的第一部分与第一TCAM级中的存储字的第一部分进行比较。 该方法还包括将第一TCAM级的输出与第二TCAM级的输入进行接口。 该方法还包括当搜索词的第一部分与存储的单词的第一部分匹配时，在第二TCAM阶段中将搜索词的第二部分与所存储的单词的第二部分进行比较。 第一个TCAM阶段与第二个TCAM阶段不同。

公开(公告)号：US10049729B1

公开(公告)日：2018-08-14

申请号：US15708393

申请日：2017-09-19

Applicant: QUALCOMM Incorporated

Inventor： Esin Terzioglu ,  Sei Seung Yoon ,  Chulmin Jung ,  Bin Liang

IPC: G11C11/00 ,  G11C11/419

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may change a device operating voltage from a first voltage to a second voltage while the assist circuit is in a first state. The apparatus may also maintain the device operating voltage at the second voltage for a predetermined time. The apparatus may switch the assist circuit from the first state to a second state. The apparatus may adjust the device operating voltage to a third voltage after the predetermined time, wherein the second voltage is a voltage level between the first voltage and the third voltage. By transitioning the device operating voltage from the first voltage to the third voltage while at the same time preventing the assist circuit from entering particular read assist states, the apparatus may reduce a likelihood of read failures.

公开(公告)号：US09984029B2

公开(公告)日：2018-05-29

申请号：US14484137

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： Kern Rim ,  Stanley Seungchul Song ,  Xiangdong Chen ,  Raymond George Stephany ,  John Jianhong Zhu ,  Ohsang Kwon ,  Esin Terzioglu ,  Choh Fei Yeap

IPC: H01L23/528 ,  G06F13/40 ,  G06F13/42 ,  G06F17/50 ,  H01L27/02

CPC classification number: G06F13/4068 ,  G06F13/4221 ,  G06F17/5068 ,  G06F17/5077 ,  H01L23/528 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of designing conductive interconnects includes determining a residual spacing value based at least in part on an integer multiple of a interconnect trace pitch and a designated cell height. The method also includes allocating the residual spacing to at least one interconnect trace width or interconnect trace space within the interconnect trace pitch.

公开(公告)号：US09692448B1

公开(公告)日：2017-06-27

申请号：US15273621

申请日：2016-09-22

Applicant: QUALCOMM Incorporated

Inventor： Xiaohua Kong ,  Mohamed Allam ,  Esin Terzioglu ,  Jose Gilberto Corleto Mena

IPC: H03M9/00 ,  G05F3/16 ,  H03L7/08

CPC classification number: H03M9/00 ,  G05F3/16 ,  H01L25/18 ,  H04L7/0008

Abstract: An SoC integrated circuit package is provided in which the analog components of a SerDes for an SoC die in the SoC integrated circuit package are segregated into a SerDes interface die in the SoC integrated circuit package.

公开(公告)号：US09082481B2

公开(公告)日：2015-07-14

申请号：US14503861

申请日：2014-10-01

Applicant: QUALCOMM Incorporated

Inventor： Esin Terzioglu ,  Nishith Desai ,  Rakesh Vattikonda ,  ChangHo Jung ,  Sei Seung Yoon

IPC: G11C15/04 ,  G11C15/00

CPC classification number: G11C15/04 ,  G11C15/00 ,  G11C15/043 ,  G11C15/046

Abstract: A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor.

公开(公告)号：US20140185349A1

公开(公告)日：2014-07-03

申请号：US13730524

申请日：2012-12-28

Applicant: QUALCOMM INCORPORATED

Inventor： Esin Terzioglu ,  Nishith Desai ,  Rakesh Vattikonda ,  ChangHo Jung ,  Sei Seung Yoon

IPC: G11C15/04

CPC classification number: G11C15/04 ,  G11C15/00 ,  G11C15/043 ,  G11C15/046

Abstract: A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor.

Abstract translation: 静态三元内容可寻址存储器（TCAM）包括密钥单元和耦合到中间匹配行的掩码单元。 关键单元耦合到第一下拉晶体管和第一上拉晶体管。 掩模单元耦合到第二下拉晶体管和第二上拉晶体管。 第一下拉晶体管和第二下拉晶体管并联连接，第一上拉晶体管和第二上拉晶体管串联连接。 匹配线输出还耦合到第一下拉晶体管和第二下拉晶体管，并且还耦合到第一上拉晶体管和第二上拉晶体管。

公开(公告)号：US20130058151A1

公开(公告)日：2013-03-07

申请号：US13667187

申请日：2012-11-02

Applicant: QUALCOMM Incorporated

Inventor： Esin Terzioglu

IPC: G11C17/00 ,  G11C17/02 ,  G11C17/16

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: Read and write operations of a non-volatile memory (NVM) bitcell have different optimum parameters resulting in a conflict during design of the NVM bitcell. A single bitline in the NVM bitcell prevents optimum read performance. Read performance may be improved by splitting the read path and the write path in a NVM bitcell between two bitlines. A read bitline of the NVM bitcell has a low capacitance for improved read operation speed and decreased power consumption. A write bitline of the NVM bitcell has a low resistance to handle large currents present during write operations. A memory element of the NVM bitcell may be a fuse, anti-fuse, eFUSE, or magnetic tunnel junction. Read performance may be further enhanced with differential sensing read operations.

Abstract translation: 非易失性存储器（NVM）位单元的读写操作具有不同的最佳参数，从而在NVM位单元的设计过程中产生冲突。 NVM位单元中的单个位线阻止了最佳的读取性能。 通过将读路径和写入路径分割在两个位线之间的NVM位单元中可以提高读取性能。 NVM位单元的读取位线具有低电容，从而提高读取操作速度并降低功耗。 NVM位单元的写位线具有低电阻以处理写操作期间存在的大电流。 NVM位单元的存储元件可以是保险丝，反熔丝，eFUSE或磁性隧道结。 差分感测读取操作可以进一步增强读取性能。