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11.发明授权Multi-wire single-ended push-pull link with data symbol transition based clocking 有权多线单端推挽链路，具有基于数据符号转换的时钟公开(公告)号：US09118457B2
公开(公告)日：2015-08-25
申请号：US14205242
申请日：2014-03-11
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku , George Alan Wiley , Joseph Cheung
CPC classification number: H04L7/027 , G06F13/4072 , G06F13/4295 , H04L25/00 , H04L25/14
Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A sequence of data bits is converted into M transition numbers, which are then converted into a sequence of symbols. The sequence of symbols is transmitted received over N wires. A clock signal may be effectively embedded in the transmission of the sequence of symbols. Each of the sequence of symbols may be selected based on a corresponding one of the M transition numbers and a value of a preceding one of the sequence of symbols.
Abstract translation: 描述了便于通过多线数据通信链路，特别是在电子设备内的两个设备之间传输数据的系统，方法和装置。 数据比特序列被转换成M个转换号码，然后转换成符号序列。 通过N线接收符号序列。 可以有效地将时钟信号嵌入到符号序列的传输中。 符号序列中的每一个可以基于M个转移号码中的一个和符号序列中的前一个的值来选择。
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12.发明授权Sharing hardware resources between D-PHY and N-factorial termination networks 有权在D-PHY和N-factorial终端网络之间共享硬件资源公开(公告)号：US08970248B2
公开(公告)日：2015-03-03
申请号：US14210246
申请日：2014-03-13
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku , George Alan Wiley , Chulkyu Lee , Joseph Cheung
CPC classification number: H04L27/2071 , G06F13/4063 , G08C19/00 , H04B1/06 , H04B3/00 , H04L25/0272 , H04L25/0292 , H04L69/18
Abstract: A termination network for a receiver device is provided to support both D-PHY signaling and N-factorial signaling. The first end of each of a plurality dynamically configurable switches is coupled to a common node. A first end of each of a plurality of resistances is coupled to a second end of a corresponding switch. A plurality of terminals receive differential signals and each terminal is coupled to a corresponding second end of a resistance. Each of a plurality differential receivers is coupled between two terminals of the termination network, wherein a first differential receiver and a second differential receiver are coupled to the same two terminals, the first differential receiver is used when the differential signals use a first type of differential signal encoding, the second differential receiver is used when the differential signals use a second type of differential signal encoding.
Abstract translation: 提供用于接收机设备的终端网络以支持D-PHY信令和N阶因子信令。 多个动态可配置开关中的每一个的第一端耦合到公共节点。 多个电阻中的每一个的第一端耦合到相应开关的第二端。 多个端子接收差分信号，并且每个端子耦合到电阻的对应的第二端。 多个差分接收器中的每一个耦合在终端网络的两个终端之间，其中第一差分接收机和第二差分接收机耦合到相同的两个终端，当差分信号使用第一类型的差分时，使用第一差分接收机 信号编码时，当差分信号使用第二类型的差分信号编码时，使用第二差分接收机。
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公开(公告)号：US20140372644A1
公开(公告)日：2014-12-18
申请号：US14302365
申请日：2014-06-11
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku , George Alan Wiley , Joseph Cheung
IPC: G06F13/42 , G06F13/364
CPC classification number: G06F13/4291 , G06F13/364 , G06F13/4282 , G06F13/4295 , H04L7/0331
Abstract: System, methods and apparatus are described that include a serial bus, including a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. The bus has a first line and a second line, a first set of devices coupled to the bus and a second set of devices coupled to the bus. A method of operating the bus includes configuring the first set of devices to use the first line for data transmissions and use the second line for a first clock signal in a first mode of operation, and configuring the second set of devices to use both the first line and the second line for data transmissions while embedding a second clock signal within symbol transitions of the data transmissions in a second mode of operation.
Abstract translation: 描述了包括串行总线的系统，方法和装置，其包括用于互联集成电路（I2C）和/或相机控制接口（CCI）操作的串行总线。 总线具有第一线路和第二线路，耦合到总线的第一组设备和耦合到总线的第二组设备。 操作总线的方法包括配置第一组设备以使用第一行进行数据传输，并且在第一操作模式中使用第二行作为第一时钟信号，并且将第二组设备配置为使用第一组 线和用于数据传输的第二行，同时在第二操作模式中将第二时钟信号嵌入在数据传输的符号转换内。
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公开(公告)号：US20170220518A1
公开(公告)日：2017-08-03
申请号：US15486217
申请日：2017-04-12
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku , George Alan Wiley , Joseph Cheung
IPC: G06F13/42 , G06F13/364
CPC classification number: G06F13/4291 , G06F13/364 , G06F13/4282 , G06F13/4295 , H04L7/0331
Abstract: System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. Other described devices may be configured as a bus master or as a slave. In one method, a transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.
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15.发明申请公开(公告)号：US20150365226A1
公开(公告)日：2015-12-17
申请号：US14834219
申请日：2015-08-24
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku , George Alan Wiley , Joseph Cheung
CPC classification number: H04L7/027 , G06F13/4072 , G06F13/4295 , H04L25/00 , H04L25/14
Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A sequence of data bits is converted into M transition numbers, which are then converted into a sequence of symbols. The sequence of symbols is transmitted received over N wires. A clock signal may be effectively embedded in the transmission of the sequence of symbols. Each of the sequence of symbols may be selected based on a corresponding one of the M transition numbers and a value of a preceding one of the sequence of symbols.
Abstract translation: 描述了便于通过多线数据通信链路，特别是在电子设备内的两个设备之间传输数据的系统，方法和装置。 数据比特序列被转换成M个转换号码，然后转换成符号序列。 通过N线接收符号序列。 可以有效地将时钟信号嵌入到符号序列的传输中。 符号序列中的每一个可以基于M个转移号码中的一个和符号序列中的前一个的值来选择。
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Patent Agency Ranking
公开(公告)号：US20140286466A1
公开(公告)日：2014-09-25
申请号：US14220056
申请日：2014-03-19
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku , Joseph Cheung , George Alan Wiley
IPC: H04L7/04
CPC classification number: H04L7/0087 , H03K3/017 , H03K5/13 , H03K5/133 , H03K5/134 , H03K5/14 , H03K5/153 , H03K5/1534 , H03K19/00 , H03K2005/00293 , H03L7/081 , H04L7/0037 , H04L7/033 , H04L7/0331
Abstract: A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire open-drain link by determining a transition in a signal received from the multi-wire open-drain link, generating a clock pulse responsive to the transition, delaying the clock pulse by a preconfigured first interval if the transition is in a first direction, and delaying the clock by a preconfigured second interval if the transition is in a second direction. The preconfigured first and/or second intervals are configured based on a rise time and/or a fall time associated with the communication interface and may be calibrated by measuring respective delays associated with clock pulses generated for first and second calibration transitions.
Abstract translation: 描述了一种方法，装置和计算机程序产品。 该装置通过确定从多线开漏链路接收的信号中的转变来产生用于从多线开漏链路接收数据的接收时钟信号，响应于该转换产生时钟脉冲，延迟时钟脉冲 如果转换处于第一方向，则通过预先配置的第一间隔，并且如果转换处于第二方向，则将时钟延迟预先配置的第二间隔。 基于与通信接口相关联的上升时间和/或下降时间来配置预配置的第一和/或第二间隔，并且可以通过测量与为第一和第二校准转换产生的时钟脉冲相关联的相应延迟来校准预配置的第一和/或第二间隔。
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17.发明申请SHARING HARDWARE RESOURCES BETWEEN D-PHY AND N-FACTORIAL TERMINATION NETWORKS 有权在D-PHY和N-FACTORY终止网络之间共享硬件资源公开(公告)号：US20140270005A1
公开(公告)日：2014-09-18
申请号：US14210246
申请日：2014-03-13
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku , George Alan Wiley , Chulkyu Lee , Joseph Cheung
IPC: H04L27/20
CPC classification number: H04L27/2071 , G06F13/4063 , G08C19/00 , H04B1/06 , H04B3/00 , H04L25/0272 , H04L25/0292 , H04L69/18
Abstract: A termination network for a receiver device is provided to support both D-PHY signaling and N-factorial signaling. The first end of each of a plurality dynamically configurable switches is coupled to a common node. A first end of each of a plurality of resistances is coupled to a second end of a corresponding switch. A plurality of terminals receive differential signals and each terminal is coupled to a corresponding second end of a resistance. Each of a plurality differential receivers is coupled between two terminals of the termination network, wherein a first differential receiver and a second differential receiver are coupled to the same two terminals, the first differential receiver is used when the differential signals use a first type of differential signal encoding, the second differential receiver is used when the differential signals use a second type of differential signal encoding.
Abstract translation: 提供用于接收机设备的终端网络以支持D-PHY信令和N阶因子信令。 多个动态可配置开关中的每一个的第一端耦合到公共节点。 多个电阻中的每一个的第一端耦合到相应开关的第二端。 多个端子接收差分信号，并且每个端子耦合到电阻的对应的第二端。 多个差分接收器中的每一个耦合在终端网络的两个终端之间，其中第一差分接收机和第二差分接收机耦合到相同的两个终端，当差分信号使用第一类型的差分时，使用第一差分接收机 信号编码时，当差分信号使用第二类型的差分信号编码时，使用第二差分接收机。
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18.发明申请公开(公告)号：US20140254732A1
公开(公告)日：2014-09-11
申请号：US14199898
申请日：2014-03-06
Applicant: QUALCOMM INCORPORATED
Inventor： Shoichiro Sengoku , George Alan Wiley , Chulkyu Lee , Joseph Cheung
IPC: H04L7/033
CPC classification number: H04L7/033 , H03K5/1252 , H03K5/1534 , H04L7/0066 , H04L7/027 , H04L25/0272 , H04L25/14 , H04L25/49 , H04L25/4906 , H04L25/493
Abstract: A method for performing multi-wire signaling encoding is provided in which a clock signal is encoded within symbol transitions. A sequence of data bits is converted into a plurality of m transition numbers. Each transition number is converted into a sequential symbol number from a set of sequential symbol numbers. The sequential symbol number is converted into a raw symbol that can be transmitted over a plurality of differential drivers. The raw symbol is transmitted spread over a plurality of n wires, wherein the clock signal is effectively embedded in the transmission of raw symbols since the conversion from transition number into a sequential symbol number guarantees that no two consecutive raw symbols are the same. The raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the plurality of n wires.
Abstract translation: 提供了一种用于执行多线信令编码的方法，其中在符号转换内对时钟信号进行编码。 数据位序列被转换成多个m个转换数。 每个转换编号从一组顺序符号编号转换成顺序符号。 顺序符号号被转换成可以通过多个差分驱动器发送的原始符号。 原始符号被传播扩展到多条n线，其中时钟信号被有效地嵌入到原始符号的传输中，因为从转换数转换为顺序符号，从而确保没有两个连续的原始符号相同。 原始符号保证在多条n线的所有对上具有非零的差分电压。
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公开(公告)号：US10511842B2
公开(公告)日：2019-12-17
申请号：US15727517
申请日：2017-10-06
Applicant: QUALCOMM INCORPORATED
Inventor： Meghal Varia , Serag Gadelrab , Wesley James Holland , Joseph Cheung , Dam Backer , Tom Longo
IPC: G06K9/00 , H04N19/162 , H04N19/12 , H04N19/172 , H04N19/46 , H04N5/917 , G06F12/02 , H04N19/119 , H04N19/115 , H04N19/174 , H04N19/167
Abstract: An exemplary method for intelligent compression uses a foveated-compression approach. First, the location of a fixation point within an image frame is determined. Next, the image frame is sectored into two or more sectors such that one of the two or more sectors is designated as a fixation sector and the remaining sectors are designated as foveation sectors. A sector may be defined by one or more tiles within the image frame. The fixation sector includes the particular tile that contains the fixation point and is compressed according to a lossless compression algorithm. The foveation sectors are compressed according to lossy compression algorithms. As the locations of foveation sectors increase in angular distance from the location of the fixation sector, a compression factor may be increased.
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20.发明申请公开(公告)号：US20180048817A1
公开(公告)日：2018-02-15
申请号：US15237413
申请日：2016-08-15
Applicant: QUALCOMM Incorporated
Inventor： Suolong Dong , Scott Cheng , Jeffrey Chu , Neil Christanto , Joseph Cheung , Michael Lee Coulter , Chia-Yuan Teng , Haoping Xu
CPC classification number: H04N5/23241 , G06K9/6202 , G06T1/20 , G06T3/4015 , G06T2207/10024 , H04N1/2112 , H04N5/23293 , H04N19/132
Abstract: Methods and apparatus improve static region detection in an imaging pipeline. An imaging pipeline may perform detection of static regions of an image at multiple stages of the pipeline. For example, as static regions may be eliminated from further processing by the imaging pipeline, static region detection performed at an early stage of the pipeline may provide for maximized power savings. As images early in the pipeline may contain artifacts inhibiting detection of some static regions, additional static region detection may be performed after further image processing. For example, static region detection may be performed for a second time after some filtering is applied to images in the pipeline. Regions previously characterized as dynamic may be characterized as static later in the pipeline due to a reduction of noise for example provided by the filters, and differences between the static region detection at different positions within the imaging pipeline.
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