公开(公告)号：US20150355033A1

公开(公告)日：2015-12-10

申请号：US14300110

申请日：2014-06-09

Applicant: QUALCOMM Incorporated

Inventor： Junmou Zhang ,  Chuang Zhang ,  Nan Chen

IPC: G01K7/01 ,  G01K13/00

CPC classification number: G01K7/015 ,  G01K13/00 ,  G01K15/005

Abstract: Systems and methods for sensing temperature on a chip are described herein. In one embodiment, a temperature sensor comprises a first transistor having a gate, a second transistor having a gate coupled to the gate of the first transistor, and a bias circuit configured to bias the gates of the first and second transistors such that the first and second transistors operate in a sub-threshold region, and to generate a current proportional to a difference between a gate-to-source voltage of the first transistor and a gate-to-source voltage of the second transistor. The temperature sensor also comprises an analog-to-digital converter (ADC) configured to convert the current into a digital temperature reading

Abstract translation: 本文描述了用于感测芯片上的温度的系统和方法。 在一个实施例中，温度传感器包括具有栅极的第一晶体管，具有耦合到第一晶体管的栅极的栅极的第二晶体管，以及被配置为偏置第一和第二晶体管的栅极的偏置电路， 第二晶体管在子阈值区域中工作，并且产生与第一晶体管的栅极 - 源极之间的电压和第二晶体管的栅极 - 源极间电压之间的差成比例的电流。 温度传感器还包括被配置为将电流转换成数字温度读数的模拟 - 数字转换器（ADC）

公开(公告)号：US20150311875A1

公开(公告)日：2015-10-29

申请号：US14261161

申请日：2014-04-24

Applicant: QUALCOMM Incorporated

Inventor： Nan Chen ,  Yu Song ,  Terrence Brian Remple ,  Yuehchun Claire Cheng

IPC: H03F3/45

CPC classification number: G11C7/065 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/225

Abstract: Sense amplifiers that can provide improved resolving times can be used, for example, in clock and data recovery circuits. The sense amplifiers sense the value of a differential input signal using a latch circuit and then, after an initial sensing time, force the latch circuit to resolve a digital value that corresponds to the value of the input signal. An implementation of the sense amplifies uses a first latch with cross-coupled inverters that produce set and reset signals. A transistor pair couples the differential input signal to the cross-coupled inverters via a switch to ground. A discharge path circuit arranged to accelerate the resolving of the latch circuit is also coupled to the cross-coupled inverters. The discharge path can be enabled after an initial sensing time.

Abstract translation: 可以提供可以提供改善的分辨时间的感测放大器，例如在时钟和数据恢复电路中。 感测放大器使用锁存电路感测差分输入信号的值，然后在初始感测时间之后强制锁存电路解析与输入信号的值对应的数字值。 感测放大器的实现使用具有产生设置和复位信号的交叉耦合反相器的第一锁存器。 晶体管对将差分输入信号通过开关接地耦合到交叉耦合的反相器。 布置成加速锁存电路的分辨率的放电路径电路也耦合到交叉耦合的反相器。 放电路径可以在初始检测时间后启用。

公开(公告)号：US20180034452A1

公开(公告)日：2018-02-01

申请号：US15271007

申请日：2016-09-20

Applicant: QUALCOMM Incorporated

Inventor： Shan Lu ,  Nan Chen ,  Min Chen

IPC: H03K5/156 ,  H03K21/02 ,  H03K3/03

CPC classification number: H03K5/1565 ,  G01R31/31725 ,  H03K3/0315 ,  H03K21/026

Abstract: Methods and systems for independently tracking NMOS device process variation and PMOS device process variation are described herein. In one embodiment, a method for tracking process variation includes measuring a frequency of an NMOS-based ring oscillator on a chip, and determining a threshold voltage or switching speed for NMOS transistors on the chip based on the measured frequency of the NMOS-based ring oscillator. The method also includes measuring a frequency of a PMOS-based ring oscillator on the chip, and determining a threshold voltage or switching speed for PMOS transistors on the chip based on the measured frequency of the PMOS-based ring oscillator.

公开(公告)号：US09484892B1

公开(公告)日：2016-11-01

申请号：US14850801

申请日：2015-09-10

Applicant: QUALCOMM Incorporated

Inventor： Mohammad Reza Kakoee ,  Shih-Hsin Jason Hu ,  Min Chen ,  Jasmin Smaila Ibrahimovic ,  Carlos Auyon ,  Sorin Adrian Dobre ,  Navid Toosizadeh ,  Nan Chen ,  Mohamed Waleed Allam

IPC: G01R31/317 ,  H03K3/011 ,  H03K3/012

CPC classification number: H03K3/011 ,  G01R31/2884 ,  G01R31/31727 ,  H03K3/012

Abstract: An integrated circuit compensates for circuit aging by measuring the aging with an aging sensor and controlling a supply voltage based on the measured aging. The operating environment for the aging sensor can be set to reduce impacts of non-aging effects on the measured aging. For example, the operating environment can use a temperature inversion voltage. An initial aging measurement value which is the difference between an initial aged measurement and an initial unaged measurement can be stored on the integrated circuit. A core power reduction controller can use the measured aging and the stored initial aging measurement value to update a performance-sensor target value and then perform adaptive voltage scaling using the using the updated performance-sensor target value.

Abstract translation: 集成电路通过使用老化传感器测量老化并根据测量的老化来控制电源电压来补偿电路老化。 老化传感器的操作环境可以设置为减少非老化对测量老化的影响。 例如，操作环境可以使用温度反转电压。 初始老化测量值与初始未老化测量值之差可以存储在集成电路上。 核心功率降低控制器可以使用测量的老化和存储的初始老化测量值来更新性能传感器目标值，然后使用更新的性能传感器目标值来执行自适应电压缩放。

公开(公告)号：US20150318978A1

公开(公告)日：2015-11-05

申请号：US14268850

申请日：2014-05-02

Applicant: QUALCOMM Incorporated

Inventor： Yu Song ,  Jan Christian Diffenderfer ,  Nan Chen ,  David Ian West ,  Paul Lawrence Viani

IPC: H04L7/00 ,  H03L7/091

CPC classification number: H04L7/0016 ,  H03L7/0807 ,  H03L7/091 ,  H04L7/0083 ,  H04L7/0338

Abstract: Systems and methods for recovering clock and data from a data input signal are disclosed that sample a plurality of clock phase signals with the data input signal to determine a timing relationship between the data input signal and the clock phase signals and use the determined to timing relationship to select one of the clock phase signals to use for sampling the data input signal to produce recovered data. The CDR can include a glitch suppression module to suppress glitches on the clock output signal that could be caused by large instantaneous jitter on the data input signal. A clock and data recovery circuit (CDR) using these methods can quickly lock to a new data input signal and can reliably receive data when there is large instantaneous timing jitter on the data input signal.

Abstract translation: 公开了用于从数据输入信号恢复时钟和数据的系统和方法，用数据输入信号对多个时钟相位信号进行采样，以确定数据输入信号和时钟相位信号之间的定时关系，并使用确定的定时关系 选择一个时钟相位信号用于采样数据输入信号以产生恢复的数据。 CDR可以包括毛刺抑制模块，以抑制可能由数据输入信号上的大的瞬时抖动引起的时钟输出信号的毛刺。 使用这些方法的时钟和数据恢复电路（CDR）可以快速锁定到新的数据输入信号，并且可以在数据输入信号上存在大的瞬时定时抖动时可靠地接收数据。

公开(公告)号：US20150109034A1

公开(公告)日：2015-04-23

申请号：US14056861

申请日：2013-10-17

Applicant: QUALCOMM INCORPORATED

Inventor： Narasimhan Vasudevan ,  Zhiqin Chen ,  Li Pan ,  Michael Thomas Fertsch ,  Nan Chen

IPC: H03L7/08

CPC classification number: H03L7/0995 ,  G11C7/222 ,  H03L7/0805 ,  H03L7/0816

Abstract: A delay architecture for reducing downtime during frequency switching is described herein. In one embodiment, an adjustable delay circuit comprises a phase-locked loop (PLL) or a delay-locked loop (DLL) configured to generate a bias voltage, and a plurality of delay elements coupled in series, wherein each of the delay elements is biased by the bias voltage. The adjustable delay circuit also comprises a multiplexer coupled to outputs of two or more of the delay elements, wherein each of the outputs corresponds to a different delay of an input signal, and wherein the multiplexer is configured to select one of the outputs based on a data frequency of a memory interface.

Abstract translation: 这里描述了用于在频率切换期间减少停机时间的延迟架构。 在一个实施例中，可调延迟电路包括被配置为产生偏置电压的锁相环（PLL）或延迟锁定环（DLL）以及串联耦合的多个延迟元件，其中每个延迟元件是 由偏置电压偏置。 可调延迟电路还包括耦合到两个或更多个延迟元件的输出的多路复用器，其中每个输出对应于输入信号的不同延迟，并且其中多路复用器被配置为基于 存储器接口的数据频率。

公开(公告)号：US10382034B2

公开(公告)日：2019-08-13

申请号：US15358494

申请日：2016-11-22

Applicant: QUALCOMM Incorporated

Inventor： Guoan Zhong ,  Junmou Zhang ,  Nan Chen

IPC: H03K17/687 ,  H03K19/21 ,  H03K3/03 ,  G06F1/324 ,  G01R19/252 ,  G06F1/32

Abstract: An apparatus for sensing distributed load currents provided by power gating circuit. The apparatus includes a power gating circuit including a set of bulk transistors coupled in series with a set of circuits between first and second voltage rails. The apparatus includes a current sensor with a first ring oscillator, a first frequency-to-code (FTC) converter, a second ring oscillator, a second FTC converter, and a subtractor. The first ring oscillator includes a first set of one or more inverters configured to receive a first voltage at a node between the power gating circuit and the first circuit, and a second set of one or more inverters configured to receive a second voltage at a second node between the power gating circuit and the second circuit. The first ring oscillator is configured to generate a signal including a frequency related to the voltage drops across the first and second sets of transistors.

公开(公告)号：US09903892B2

公开(公告)日：2018-02-27

申请号：US14480321

申请日：2014-09-08

Applicant: QUALCOMM Incorporated

Inventor： Chuang Zhang ,  Nan Chen ,  Junmou Zhang

IPC: G01R19/252 ,  G01R23/10 ,  H03M1/06 ,  H03M1/12 ,  H03M1/60

CPC classification number: G01R19/252 ,  G01R23/10 ,  H03M1/0607 ,  H03M1/1295 ,  H03M1/60

Abstract: In one embodiment, a method for measuring current comprises generating a sensor current based on a current being measured. The method also comprises converting a combined current into a first frequency, wherein the combined current is a sum of the sensor current and a common-mode current, and converting the first frequency into a first count value. The method further comprises converting the common-mode current into a second frequency, converting the second frequency into a second count value, and subtracting the second count value from the first count value to obtain a current reading.

公开(公告)号：US09671438B2

公开(公告)日：2017-06-06

申请号：US14533950

申请日：2014-11-05

Applicant: QUALCOMM Incorporated

Inventor： Chuang Zhang ,  Zhengming Fu ,  Nan Chen

IPC: G01R19/25 ,  G01R19/32 ,  G01R19/00

CPC classification number: G01R19/25 ,  G01R19/0092 ,  G01R19/32

Abstract: In one embodiment, a method for measuring current is described herein. The method comprises shorting first and second inputs of an amplifying circuit to generate a first output signal, and converting the first output signal into an offset cancelation value. The method also comprises passing a current through a power switch, wherein the current generates a voltage drop across the power switch, applying the voltage drop across the first and second inputs of the amplifying circuit to generate a second output signal, and converting the second output signal into a current value. The method further comprises subtracting the offset cancelation value from the current value to generate an offset-compensated current value.

公开(公告)号：US09645602B2

公开(公告)日：2017-05-09

申请号：US14863221

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Junmou Zhang ,  Nan Chen ,  Guoan Zhong

IPC: G06F1/08 ,  G06F11/00 ,  G06F21/55

CPC classification number: G06F1/08 ,  G06F21/554 ,  G06F2221/034 ,  H04L9/004 ,  H04L9/005

Abstract: A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus may be used for detecting an incorrect clock frequency. In one example, the apparatus includes a first circuit configured to compare a clock signal period to a delay period. Additionally, in one example, the apparatus includes a second circuit configured to output a first signal. The period of the first signal may be double the clock signal period when the clock signal period is greater than the delay period. The apparatus may, in one example, also include a third circuit configured to output a second signal. The period of the second signal may be greater than double the clock signal period when the clock signal period is greater than the delay period.