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    Method And Apparatus For A Shared Cache With Dynamic Partitioning
    12.
    发明申请
    Method And Apparatus For A Shared Cache With Dynamic Partitioning 审中-公开
    用于动态分区的共享缓存的方法和装置

    公开(公告)号：US20160019158A1

    公开(公告)日：2016-01-21

    申请号：US14334010

    申请日：2014-07-17

    Applicant: QUALCOMM Incorporated

    Inventor： Subbarao Palacharla ,  Moinul Khan ,  Alain Artieri ,  Kedar Bhole ,  Vinod Chamarty ,  Yanru Li ,  Raghu Sankuratri ,  George Patsilaras ,  Pavan Kumar Thirunagari ,  Andrew Edward Turner ,  Jeong-Ho Woo

    IPC: G06F12/08

    CPC classification number: G06F12/0893 ,  G06F1/3203 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/50 ,  G06F12/084 ,  G06F12/0864 ,  G06F12/0888 ,  G06F12/0895 ,  G06F17/30902 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/601 ,  G06F2212/6042 ,  Y02D10/13

    Abstract: Aspects include computing devices, systems, and methods for dynamically partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests and reserve locations in the system cache corresponding to the component caches correlated with component cache identifiers of the requests. Reserving locations in the system cache may activate the locations in the system cache for use by a requesting client, and may also prevent other client from using the reserved locations in the system cache. Releasing the locations in the system cache may deactivate the locations in the system cache and allow other clients to use them. A client reserving locations in the system cache may change the amount of locations it has reserved within its component cache.

    Abstract translation: 方面包括计算设备，系统和方法，用于通过集合和方式动态地将系统高速缓存分区到组件高速缓存中。 系统高速缓冲存储器控制器可以管理组件高速缓存并管理对组件高速缓存的访问。 系统高速缓冲存储器控制器可以接收系统高速缓存访​​问请求，并且在系统高速缓存中保留对应于与请求的组件高速缓存标识符相关联的组件高速缓存的位 在系统缓存中预留位置可以激活系统高速缓存中的位置以供请求客户端使用，并且还可以防止其他客户端使用系统高速缓存中的保留位置。 释放系统缓存中的位置可以停用系统缓存中的位置，并允许其他客户端使用它们。 保留系统缓存中的位置的客户端可以改变其在其组件高速缓存中保留的位置的数量。

    HIERARCHICAL POWER ESTIMATION AND THROTTLING IN A PROCESSOR-BASED SYSTEM IN AN INTEGRATED CIRCUIT (IC) CHIP
    13.
    发明申请
    HIERARCHICAL POWER ESTIMATION AND THROTTLING IN A PROCESSOR-BASED SYSTEM IN AN INTEGRATED CIRCUIT (IC) CHIP 有权

    公开(公告)号：US20240427410A1

    公开(公告)日：2024-12-26

    申请号：US18339422

    申请日：2023-06-22

    Applicant: QUALCOMM Incorporated

    Inventor： Vinod Chamarty ,  Sagar Koorapati ,  Alon Naveh

    IPC: G06F1/3293

    Abstract: Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well as integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. To mitigate the delay in the reporting of activity power event of a monitored processing device that may affect throttling of power consumption for the IC chip, the power consumption of a monitored processing device can also be throttled locally throttle its power consumption. This gives reaction time for the power management system to receive and process activity power events to throttle power consumption in the IC chip.

    TRACING CIRCUIT INCLUDING MEMORY MAPPED TRACE BUFFERS IN NODES OF A MESH NETWORK
    14.
    发明公开
    TRACING CIRCUIT INCLUDING MEMORY MAPPED TRACE BUFFERS IN NODES OF A MESH NETWORK 审中-公开

    公开(公告)号：US20240320125A1

    公开(公告)日：2024-09-26

    申请号：US18528225

    申请日：2023-12-04

    Applicant: QUALCOMM Incorporated

    Inventor： Gaurav Sanjeev Kirtane ,  Vinod Chamarty

    IPC: G06F11/34

    CPC classification number: G06F11/348 ,  G06F11/3495

    Abstract: Tracing circuits are disposed within each node circuit in a mesh network to debug problems found during development. The tracing circuit disclosed includes a trace read interface for accessing trace packets stored in a trace buffer at entries that are mapped to system memory addresses. Processing circuits coupled to the trace read interface may access the stored trace packets using memory instructions. The trace packets include trace information generated from packets that are detected on selected ports of a node circuit in a node of the mesh network. A filter circuit compares the transaction units to a trace criteria and stores the trace information of the matching packets in the form of trace packets in the memory-mapped entries of the trace buffer. The trace packets can include the transaction units of a packet or just packet header information for more efficient use of the trace buffer.

    ROUTING RAW DEBUG DATA USING TRACE INFRASTRUCTURE IN PROCESSOR-BASED DEVICES
    15.
    发明公开
    ROUTING RAW DEBUG DATA USING TRACE INFRASTRUCTURE IN PROCESSOR-BASED DEVICES 审中-公开

    公开(公告)号：US20240202087A1

    公开(公告)日：2024-06-20

    申请号：US18498583

    申请日：2023-10-31

    Applicant: QUALCOMM Incorporated

    Inventor： Sreeram Jayadev ,  Vinod Chamarty

    IPC: G06F11/22

    CPC classification number: G06F11/2221

    Abstract: Routing raw debug data using trace infrastructure in processor-based devices is disclosed. In some aspects, a processor-based device comprises a trace interconnect bus, a subsystem circuit comprising a debug transmit circuit, and an input/output (I/O) endpoint circuit. The debug transmit circuit is configured to receive raw debug data from the subsystem circuit, and generate a debug trace packet comprising the raw debug data in lieu of formatted trace data. The debug transmit circuit is also configured to transmit the debug trace packet comprising the raw debug data to the I/O endpoint circuit via the trace interconnect bus during a period of trace interconnect bus inactivity. In this manner, an existing trace infrastructure can be employed to transmit raw debug data without incurring expense in terms of overhead and monetary cost due to the need for industry-standard, infrastructure-compliant tools to decode conventionally packetized trace data for analysis.

    INTEGRATED CIRCUITS (IC) CHIPS INCLUDING THROTTLE REQUEST ACCUMULATE CIRCUITS FOR CONTROLLING POWER CONSUMED IN PROCESSING CIRCUITS AND RELATED METHODS
    17.
    发明申请
    INTEGRATED CIRCUITS (IC) CHIPS INCLUDING THROTTLE REQUEST ACCUMULATE CIRCUITS FOR CONTROLLING POWER CONSUMED IN PROCESSING CIRCUITS AND RELATED METHODS 有权

    公开(公告)号：US20240427397A1

    公开(公告)日：2024-12-26

    申请号：US18339447

    申请日：2023-06-22

    Applicant: QUALCOMM Incorporated

    Inventor： Sagar Koorapati ,  Vinod Chamarty ,  Gaurav Sanjeev Kirtane ,  Pushkin Raj Pari ,  Nitin Makhija ,  Alon Naveh

    IPC: G06F1/28

    Abstract: The processor-based system includes a throttle request accumulate circuit to receive throttle requests, determine a highest or most aggressive throttle value among the throttle requests, and generate a throttle control signal configured to throttle activity in the plurality of processing circuits. Throttle requests have throttle values corresponding to a reduction in activity in at least a portion of the plurality of processing circuits and may correspond to a particular number of cycles of reduced activity in a window of cycles. In addition to reducing response time to local events or conditions compared to waiting for a hierarchical response, the throttle request accumulate circuit accumulates throttle requests from all circuits that adjust or throttle activity in the plurality of processing circuits, and ensures that the net effective throttle controlling activity in the processing circuits at any given time is based on the highest throttle value of those accumulated throttle requests.

    DETECTING AND RECOVERING FROM TIMEOUTS IN SCALABLE MESH NETWORKS IN PROCESSOR-BASED DEVICES
    18.
    发明公开
    DETECTING AND RECOVERING FROM TIMEOUTS IN SCALABLE MESH NETWORKS IN PROCESSOR-BASED DEVICES 审中-公开

    公开(公告)号：US20240362103A1

    公开(公告)日：2024-10-31

    申请号：US18594858

    申请日：2024-03-04

    Applicant: QUALCOMM Incorporated

    Inventor： Gaurav Sanjeev Kirtane ,  Vinod Chamarty ,  Vignesh Deivaraj

    IPC: G06F11/07 ,  G06F11/30

    CPC classification number: G06F11/0772 ,  G06F11/0757 ,  G06F11/3027

    Abstract: Detecting and recovering from timeouts in scalable mesh circuits in processor-based devices is disclosed herein. In some exemplary aspects, a processor-based device provides an integrated circuit (IC) that includes an interconnect comprising a scalable mesh network communicatively coupled to a plurality of agents via a respective plurality of bridge devices. The plurality of agents includes a source agent and a target agent that communicate with a source bridge device and a target bridge device, respectively. The target bridge device receives a transaction directed to the target agent from the source agent via the interconnect. Upon receiving the transaction, the target bridge device initiates a timeout counter. If no response to the transaction received by the target bridge device from the target agent by the time the timeout counter expires, the target bridge device transmits to the source bridge device an indication that no response to the transaction was received.

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