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公开(公告)号：US20180219704A1
公开(公告)日：2018-08-02
申请号：US15422050
申请日：2017-02-01
Applicant: QUALCOMM Incorporated
Inventor： Yu Song , Zhi Zhu , Miao Li , Li Sun , Deqiang Song , Chia Heng Chang
CPC classification number: H04L25/03273 , H03L7/0814 , H04L7/0025 , H04L7/0337 , H04L43/16 , H04L2027/0069
Abstract: Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).
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公开(公告)号：US20150311875A1
公开(公告)日：2015-10-29
申请号：US14261161
申请日：2014-04-24
Applicant: QUALCOMM Incorporated
Inventor： Nan Chen , Yu Song , Terrence Brian Remple , Yuehchun Claire Cheng
IPC: H03F3/45
CPC classification number: G11C7/065 , G11C7/1084 , G11C7/1087 , G11C7/225
Abstract: Sense amplifiers that can provide improved resolving times can be used, for example, in clock and data recovery circuits. The sense amplifiers sense the value of a differential input signal using a latch circuit and then, after an initial sensing time, force the latch circuit to resolve a digital value that corresponds to the value of the input signal. An implementation of the sense amplifies uses a first latch with cross-coupled inverters that produce set and reset signals. A transistor pair couples the differential input signal to the cross-coupled inverters via a switch to ground. A discharge path circuit arranged to accelerate the resolving of the latch circuit is also coupled to the cross-coupled inverters. The discharge path can be enabled after an initial sensing time.
Abstract translation: 可以提供可以提供改善的分辨时间的感测放大器，例如在时钟和数据恢复电路中。 感测放大器使用锁存电路感测差分输入信号的值，然后在初始感测时间之后强制锁存电路解析与输入信号的值对应的数字值。 感测放大器的实现使用具有产生设置和复位信号的交叉耦合反相器的第一锁存器。 晶体管对将差分输入信号通过开关接地耦合到交叉耦合的反相器。 布置成加速锁存电路的分辨率的放电路径电路也耦合到交叉耦合的反相器。 放电路径可以在初始检测时间后启用。
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公开(公告)号：US20140199948A1
公开(公告)日：2014-07-17
申请号：US13740539
申请日：2013-01-14
Applicant: QUALCOMM INCORPORATED
Inventor： Jan Diffenderfer , Yu Song
IPC: G05F1/46
CPC classification number: G05F1/46 , H03K3/3565 , H03K19/018521
Abstract: A single-ended comparator is disclosed herein. The comparator may be implemented with low-voltage semiconductor devices that are capable of operating with high-voltage signals at an input. The single-ended comparator may be integrated in a larger circuit to receive and detect information provided on the input at voltage levels higher than the levels supported by the rest of the circuit, and transfer the information in the received signal for use by the rest of the circuit.
Abstract translation: 本文公开了单端比较器。 比较器可以利用能够在输入处与高电压信号一起工作的低压半导体器件来实现。 单端比较器可以集成在更大的电路中，以接收和检测在电路电平上提供的信号，该电平高于由电路其余部分支持的电平，并传送接收信号中的信息供其余部分使用 电路。
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公开(公告)号：US12088303B1
公开(公告)日：2024-09-10
申请号：US18173679
申请日：2023-02-23
Applicant: QUALCOMM Incorporated
CPC classification number: H03K5/01 , G06F1/06 , H03K2005/00019 , H03K2005/00286
Abstract: A clock generation apparatus has a delay circuit, a phase selection circuit, and a phase measurement circuit. The delay circuit outputs a first signal that is a delayed version of an input signal. The phase selection circuit receives the input signal and one or more phase-shifted versions of the input signal and outputs a second signal that is a phase-shifted version of the input signal. The phase measurement circuit compares the phases of the first signal and the second signal and provides a first output that controls phase of the second signal relative to the input signal. The phase measurement circuit also provides a second output that controls a delay applied by the delay circuit to the input signal to generate the first signal.
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Patent Agency Ranking
公开(公告)号：US12052023B1
公开(公告)日：2024-07-30
申请号：US18158662
申请日：2023-01-24
Applicant: QUALCOMM Incorporated
CPC classification number: H03L7/187 , H03L7/093 , H03L7/0992
Abstract: A clock recovery circuit includes a frequency tracking loop including a first charge pump, and a phase tracking loop including a second charge pump. A voltage-controlled oscillator responds to the frequency tracking loop in a first operating mode and to the phase tracking loop in a second operating mode. A lock detector outputs an activation signal that indicates whether the clock recovery circuit has acquired frequency lock. A loop filter coupled to an input of the voltage-controlled oscillator includes a switchable resistor and a programmable delay element responsive to the activation signal. The first charge pump is disabled when the activation signal indicates frequency lock has been acquired, and disabled when the activation signal indicates frequency lock has not been acquired. The switchable resistor is bypassed when an output of the programmable delay element is in the first signaling state.
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16.发明授权公开(公告)号：US09281934B2
公开(公告)日：2016-03-08
申请号：US14268850
申请日：2014-05-02
Applicant: QUALCOMM Incorporated
Inventor： Yu Song , Jan Christian Diffenderfer , Nan Chen , David Ian West , Paul Lawrence Viani
CPC classification number: H04L7/0016 , H03L7/0807 , H03L7/091 , H04L7/0083 , H04L7/0338
Abstract: Systems and methods for recovering clock and data from a data input signal are disclosed that sample a plurality of clock phase signals with the data input signal to determine a timing relationship between the data input signal and the clock phase signals and use the determined to timing relationship to select one of the clock phase signals to use for sampling the data input signal to produce recovered data. The CDR can include a glitch suppression module to suppress glitches on the clock output signal that could be caused by large instantaneous jitter on the data input signal. A clock and data recovery circuit (CDR) using these methods can quickly lock to a new data input signal and can reliably receive data when there is large instantaneous timing jitter on the data input signal.
Abstract translation: 公开了用于从数据输入信号恢复时钟和数据的系统和方法，用数据输入信号对多个时钟相位信号进行采样，以确定数据输入信号和时钟相位信号之间的定时关系，并使用确定的定时关系 选择一个时钟相位信号用于采样数据输入信号以产生恢复的数据。 CDR可以包括毛刺抑制模块，以抑制可能由数据输入信号上的大的瞬时抖动引起的时钟输出信号的毛刺。 使用这些方法的时钟和数据恢复电路（CDR）可以快速锁定到新的数据输入信号，并且可以在数据输入信号上存在大的瞬时定时抖动时可靠地接收数据。
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17.发明申请LOW-POWER, SELF-BIASING-CAPABLE CHARGE PUMP WITH CURRENT MATCHING CAPABILITIES 审中-公开具有电流匹配能力的低功耗自动充电充电泵公开(公告)号：US20150200588A1
公开(公告)日：2015-07-16
申请号：US14157100
申请日：2014-01-16
Applicant: QUALCOMM Incorporated
Inventor： Yuehchun Claire Cheng , Jan Christian Diffenderfer , Yu Song
IPC: H02M3/07
CPC classification number: H03L7/0896 , H03L7/0895
Abstract: A charge pump is disclosed herein that includes an output node configured to be coupled to a charge storage device configured to store a charge to produce a control voltage based on the charge stored in the charge storage device; a charging circuit configured to provide charge to the charge storage device; a discharging circuit configured to remove charge from the charge storage device; and an amplifier. The amplifier includes an inverting input configured to receive the control voltage from the output node as a first input signal; and, a non-inverting input configured to receive a second input signal including a bias voltage, wherein the amplifier is configured to attempt to match respective levels of the bias voltage and the control voltage when the charge in the charge storage device is changing.
Abstract translation: 本文公开了一种电荷泵，其包括被配置为耦合到电荷存储装置的输出节点，其被配置为基于存储在电荷存储装置中的电荷来存储电荷以产生控制电压; 充电电路，被配置为向所述电荷存储装置提供电荷; 放电电路，被配置为从所述电荷存储装置中去除电荷; 和放大器。 放大器包括反相输入，其被配置为从输出节点接收作为第一输入信号的控制电压; 以及配置为接收包括偏置电压的第二输入信号的非反相输入，其中所述放大器被配置为当所述电荷存储装置中的电荷改变时尝试匹配所述偏置电压和所述控制电压的各个电平。
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18.发明授权公开(公告)号：US11863356B2
公开(公告)日：2024-01-02
申请号：US17589782
申请日：2022-01-31
Applicant: QUALCOMM Incorporated
Inventor： Miao Li , Zhiqin Chen , Yu Song , Hongmei Liao , Zhi Zhu , Hao Liu , Lejie Lu
IPC: H04L25/03
CPC classification number: H04L25/03057 , H04L25/03885
Abstract: A receiver has a first equalizer circuit that includes a first stage having a source degeneration circuit and a trans-impedance amplifier (TIA). The source degeneration circuit includes a resistor coupled in parallel with a capacitor. The TIA includes an embedded variable gain amplifier with a gain controlled by feedback resistors. Each feedback resistor is coupled between input and output of the TIA. In some implementations, the receiving circuit has a second equalizer circuit coupled in series with the first equalizer circuit. The second equalizer circuit includes a first stage having a source degeneration circuit and a TIA. The source degeneration circuit in the second equalizer circuit has a source degeneration resistor coupled in parallel with a source degeneration capacitor and the TIA includes an embedded variable gain amplifier whose gain is controlled by feedback resistors coupled between input and output of the TIA in the second equalizer circuit.
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19.发明申请公开(公告)号：US20150318978A1
公开(公告)日：2015-11-05
申请号：US14268850
申请日：2014-05-02
Applicant: QUALCOMM Incorporated
Inventor： Yu Song , Jan Christian Diffenderfer , Nan Chen , David Ian West , Paul Lawrence Viani
CPC classification number: H04L7/0016 , H03L7/0807 , H03L7/091 , H04L7/0083 , H04L7/0338
Abstract: Systems and methods for recovering clock and data from a data input signal are disclosed that sample a plurality of clock phase signals with the data input signal to determine a timing relationship between the data input signal and the clock phase signals and use the determined to timing relationship to select one of the clock phase signals to use for sampling the data input signal to produce recovered data. The CDR can include a glitch suppression module to suppress glitches on the clock output signal that could be caused by large instantaneous jitter on the data input signal. A clock and data recovery circuit (CDR) using these methods can quickly lock to a new data input signal and can reliably receive data when there is large instantaneous timing jitter on the data input signal.
Abstract translation: 公开了用于从数据输入信号恢复时钟和数据的系统和方法，用数据输入信号对多个时钟相位信号进行采样，以确定数据输入信号和时钟相位信号之间的定时关系，并使用确定的定时关系 选择一个时钟相位信号用于采样数据输入信号以产生恢复的数据。 CDR可以包括毛刺抑制模块，以抑制可能由数据输入信号上的大的瞬时抖动引起的时钟输出信号的毛刺。 使用这些方法的时钟和数据恢复电路（CDR）可以快速锁定到新的数据输入信号，并且可以在数据输入信号上存在大的瞬时定时抖动时可靠地接收数据。
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