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公开(公告)号：US20140327510A1
公开(公告)日：2014-11-06
申请号：US13887788
申请日：2013-05-06
Applicant: QUALCOMM INCORPORATED
Inventor： Daeik D. Kim , David F. Berdy , Chengjie Zuo , Mario Francisco Velez , Changhan Yun , Robert P. Mikulka , Jonghae Kim , Je-Hsiung Lan
CPC classification number: H05K9/002 , H01F17/0006 , H01F27/362 , H01F2017/002 , H05K1/115 , H05K3/0017 , H05K3/107
Abstract: An electronic device includes a structure. The structure includes a first set of through glass vias (TGVs) and a second set of TGVs. The first set of TGVs includes a first via and the second set of TGVs includes a second via. The first via has a different cross-sectional shape than the second via.
Abstract translation: 一种电子设备包括一种结构。 该结构包括第一组直通玻璃通孔（TGV）和第二组TGV。 第一组TGV包括第一通孔，第二组TGV包括第二通孔。 第一通孔具有与第二通孔不同的横截面形状。
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公开(公告)号：US20140268616A1
公开(公告)日：2014-09-18
申请号：US13833632
申请日：2013-03-15
Applicant: QUALCOMM INCORPORATED
Inventor： Je-Hsiung Lan , Chengjie Zuo , Changhan Yun , David F. Berdy , Daeik D. Kim , Robert P. Mikulka , Mario Francisco Velez , Jonghae Kim
CPC classification number: H01L28/40 , G06F17/5068 , H01L23/15 , H01L23/481 , H01L23/49822 , H01L23/49827 , H01L27/016 , H01L27/12 , H01L28/10 , H01L28/60 , H01L2924/0002 , H01L2924/00
Abstract: In a particular embodiment, a device includes a substrate, a via that extends at least partially through the substrate, and a capacitor. A dielectric of the capacitor is located between the via and a plate of the capacitor, and the plate of the capacitor is external to the substrate and within the device.
Abstract translation: 在特定实施例中，器件包括衬底，至少部分延伸穿过衬底的通孔和电容器。 电容器的电介质位于电容器的通孔和板之间，并且电容器的板在衬底外部和器件内部。
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公开(公告)号：US09401689B2
公开(公告)日：2016-07-26
申请号：US13887568
申请日：2013-05-06
Applicant: QUALCOMM Incorporated
Inventor： Chengjie Zuo , Daeik D. Kim , Je-Hsiung Lan , Jonghae Kim , Mario Francisco Velez , Changhan Yun , David F. Berdy , Robert P. Mikulka , Matthew M. Nowak , Xiangdong Zhang , Puay H. See
IPC: H03H7/46
Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.
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Patent Agency Ranking
14.发明申请TUNABLE DIPLEXERS IN THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS (IC) (3DIC) AND RELATED COMPONENTS AND METHODS 有权三维（3D）集成电路（IC）（3DIC）及相关组件和方法中的可执行程序公开(公告)号：US20160204758A1
公开(公告)日：2016-07-14
申请号：US15079789
申请日：2016-03-24
Applicant: QUALCOMM Incorporated
Inventor： Chengjie Zuo , Daeik D. Kim , Je-Hsiung Lan , Jonghae Kim , Mario Francisco Velez , Changhan Yun , David F. Berdy , Robert P. Mikulka , Matthew M. Nowak , Xiangdong Zhang , Puay H. See
CPC classification number: H03H7/461 , H03H3/00 , H03H7/0115 , H03H7/463 , Y10T29/49016
Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.
Abstract translation: 公开了三维（3D）集成电路（IC）（3DIC）中的可调谐双工器。 在一个实施例中，可调谐双工器可以通过在双工器中提供变容二极管或可变电感器之一来形成。 可变电抗器或可变电感器的可变特性允许调谐双工器中的陷波，以便选择频带停止以消除期望频率处的谐波以及控制通带的截止频率。 通过将双工器的元件堆叠成三维空间是保守的，并且可以使用各种变容二极管和电感器。
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公开(公告)号：US09355967B2
公开(公告)日：2016-05-31
申请号：US13946135
申请日：2013-07-19
Applicant: QUALCOMM Incorporated
Inventor： Daeik D. Kim , Je-Hsiung Lan , Mario Francisco Velez , Chengjie Zuo , Jonghae Kim , Changhan Yun
CPC classification number: H01L23/562 , G06F17/5081 , G06F2217/80 , H01L21/02005 , H01L2924/0002 , H01L2924/3511 , H01L2924/00
Abstract: An apparatus includes a device that includes at least one layer. The at least one layer includes an inter-device stress compensation pattern configured to reduce an amount of inter-device warpage prior to the device being detached from another device.
Abstract translation: 一种装置包括包括至少一层的装置。 所述至少一个层包括设备间应力补偿模式，其被配置为在所述设备从另一设备分离之前减少设备间翘曲的量。
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公开(公告)号：US09203373B2
公开(公告)日：2015-12-01
申请号：US13798733
申请日：2013-03-13
Applicant: QUALCOMM Incorporated
Inventor： Chengjie Zuo , Jonghae Kim , Mario Francisco Velez , Je-Hsiung Lan , Daeik D. Kim , Changhan Yun , David F. Berdy , Robert P. Mikulka , Matthew M. Nowak , Xiangdong Zhang , Puay H. See
IPC: H03H7/46 , H03H3/00 , H05K1/16 , H01L23/64 , H03H1/00 , H01L23/15 , H01L23/498 , H03H7/01 , H01F17/00 , H01L23/48 , H01L23/522 , H05K1/02 , H05K1/03 , H01L23/66
CPC classification number: H03H7/461 , H01F2017/0026 , H01F2017/004 , H01L23/15 , H01L23/481 , H01L23/49827 , H01L23/5223 , H01L23/5227 , H01L23/64 , H01L23/66 , H01L2924/0002 , H03H3/00 , H03H7/1758 , H03H7/1766 , H03H7/1791 , H03H7/463 , H03H2001/0021 , H05K1/0233 , H05K1/0306 , H05K1/165 , H05K2201/09627 , H05K2201/09672 , H05K2201/10015 , H05K2201/10098 , Y10T29/49128 , H01L2924/00
Abstract: A diplexer includes a substrate having a set of through substrate vias. The diplexer also includes a first set of traces on a first surface of the substrate. The first traces are coupled to the through substrate vias. The diplexer further includes a second set of traces on a second surface of the substrate that is opposite the first surface. The second traces are coupled to opposite ends of the set of through substrate vias. The through substrate vias and the traces also operate as a 3D inductor. The diplexer also includes a capacitor supported by the substrate.
Abstract translation: 双工器包括具有一组通过衬底通孔的衬底。 双工器还包括在衬底的第一表面上的第一组迹线。 第一迹线耦合到贯穿衬底通孔。 双工器还包括与第一表面相对的在衬底的第二表面上的第二组迹线。 第二迹线耦合到该组通过衬底通孔的相对端。 贯通衬底通孔和迹线也作为3D电感器工作。 双工器还包括由基板支撑的电容器。
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公开(公告)号：US20150022264A1
公开(公告)日：2015-01-22
申请号：US13947144
申请日：2013-07-22
Applicant: QUALCOMM Incorporated
Inventor： Jung Pill Kim , Taehyun Kim , Sungryul Kim , Daeik D. Kim
CPC classification number: G01R31/2851 , G11C16/28 , G11C29/02 , G11C29/026 , G11C29/028 , G11C29/14 , G11C29/44 , G11C29/46
Abstract: A circuit includes a plurality of transistors responsive to a plurality of latches that store a test code. The circuit further includes a first bit line coupled to a data cell and coupled to a sense amplifier. The circuit also includes a second bit line coupled to a reference cell and coupled to the sense amplifier. A current from a set of the plurality of transistors is applied to the data cell via the first bit line. The set of the plurality of transistors is determined based on the test code. The circuit also includes a test mode reference circuit coupled to the first bit line and to the second bit line.
Abstract translation: 电路包括响应于存储测试码的多个锁存器的多个晶体管。 电路还包括耦合到数据单元并耦合到读出放大器的第一位线。 电路还包括耦合到参考单元并耦合到读出放大器的第二位线。 来自一组多个晶体管的电流经由第一位线被施加到数据单元。 基于测试代码来确定多个晶体管的集合。 电路还包括耦合到第一位线和第二位线的测试模式参考电路。
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公开(公告)号：US20140374914A1
公开(公告)日：2014-12-25
申请号：US13946135
申请日：2013-07-19
Applicant: QUALCOMM Incorporated
Inventor： Daeik D. Kim , Je-Hsiung Lan , Mario Francisco Velez , Chengjie Zuo , Jonghae Kim , Changhan Yun
CPC classification number: H01L23/562 , G06F17/5081 , G06F2217/80 , H01L21/02005 , H01L2924/0002 , H01L2924/3511 , H01L2924/00
Abstract: An apparatus includes a device that includes at least one layer. The at least one layer includes an inter-device stress compensation pattern configured to reduce an amount of inter-device warpage prior to the device being detached from another device.
Abstract translation: 一种装置包括包括至少一层的装置。 所述至少一个层包括设备间应力补偿模式，其被配置为在所述设备从另一设备分离之前减少设备间翘曲的量。
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