公开(公告)号：US09935166B2

公开(公告)日：2018-04-03

申请号：US13833632

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Lan ,  Chengjie Zuo ,  Changhan Yun ,  David F. Berdy ,  Daeik D. Kim ,  Robert P. Mikulka ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H05K1/16 ,  H01L49/02 ,  G06F17/50 ,  H01L23/498 ,  H01L27/01 ,  H01L23/15 ,  H01L27/12

CPC classification number: H01L28/40 ,  G06F17/5068 ,  H01L23/15 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L27/016 ,  H01L27/12 ,  H01L28/10 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a particular embodiment, a device includes a substrate, a via that extends at least partially through the substrate, and a capacitor. A dielectric of the capacitor is located between the via and a plate of the capacitor, and the plate of the capacitor is external to the substrate and within the device.

公开(公告)号：US09634640B2

公开(公告)日：2017-04-25

申请号：US13887568

申请日：2013-05-06

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Daeik D. Kim ,  Je-Hsiung Lan ,  Jonghae Kim ,  Mario Francisco Velez ,  Changhan Yun ,  David F. Berdy ,  Robert P. Mikulka ,  Matthew M. Nowak ,  Xiangdong Zhang ,  Puay H. See

IPC: H03H7/46

CPC classification number: H03H7/461 ,  H03H3/00 ,  H03H7/0115 ,  H03H7/463 ,  Y10T29/49016

Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.

公开(公告)号：US09331665B2

公开(公告)日：2016-05-03

申请号：US13887568

申请日：2013-05-06

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Daeik D. Kim ,  Je-Hsiung Lan ,  Jonghae Kim ,  Mario Francisco Velez ,  Changhan Yun ,  David F. Berdy ,  Robert P. Mikulka ,  Matthew M. Nowak ,  Xiangdong Zhang ,  Puay H. See

IPC: H03H7/46

Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.

公开(公告)号：US20140327496A1

公开(公告)日：2014-11-06

申请号：US13887568

申请日：2013-05-06

Applicant: QUALCOMM INCORPORATED

Inventor： Chengjie Zuo ,  Daeik D. Kim ,  Je-Hsiung Lan ,  Jonghae Kim ,  Mario Francisco Velez ,  Changhan Yun ,  David F. Berdy ,  Robert P. Mikulka ,  Matthew M. Nowak ,  Xiangdong Zhang ,  Puay H. See

IPC: H03H7/46 ,  H03H3/00

CPC classification number: H03H7/461 ,  H03H3/00 ,  H03H7/0115 ,  H03H7/463 ,  Y10T29/49016

Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.

Abstract translation: 公开了三维（3D）集成电路（IC）（3DIC）中的可调谐双工器。 在一个实施例中，可调谐双工器可以通过在双工器中提供变容二极管或可变电感器之一来形成。 可变电抗器或可变电感器的可变特性允许调谐双工器中的陷波，以便选择频带停止以消除期望频率处的谐波以及控制通带的截止频率。 通过将双工器的元件堆叠成三维空间是保守的，并且可以使用各种变容二极管和电感器。

公开(公告)号：US20150035162A1

公开(公告)日：2015-02-05

申请号：US13957462

申请日：2013-08-02

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Lan ,  Chengjie Zuo ,  Mario Francisco Velez ,  Daeik D. Kim ,  David F. Berdy ,  Changhan Yun ,  Robert P. Mikulka ,  Jonghae Kim ,  Matthew M. Nowak

IPC: H01L23/522 ,  G06F17/50 ,  H01L21/768

CPC classification number: H01L23/5226 ,  G06F17/5068 ,  H01F17/0013 ,  H01F41/041 ,  H01F2017/002 ,  H01L21/76897 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/13 ,  H01L28/10 ,  H01L28/40 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/13022 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H05K1/162 ,  H05K1/165 ,  H05K3/4605 ,  H01L2924/00

Abstract: An inductive device that includes a conductive via and a metal layer are disclosed. A particular method of forming an electronic device includes forming a metal layer that contacts a surface of a substrate. The substrate, including the surface, is formed from a substantially uniform dielectric material. The metal layer contacts a conductive via that extends at least partially within the substrate. The metal layer and the conductive via form at least a portion of an inductive device.

Abstract translation: 公开了一种包括导电通孔和金属层的电感器件。 形成电子器件的具体方法包括形成接触衬底表面的金属层。 包括表面的基底由基本均匀的电介质材料形成。 金属层接触至少部分地在衬底内延伸的导电通孔。 金属层和导电通孔形成电感器件的至少一部分。

公开(公告)号：US20140354372A1

公开(公告)日：2014-12-04

申请号：US14019821

申请日：2013-09-06

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Jonghae Kim ,  Daeik D. Kim ,  Mario Francisco Velez ,  Changhan Yun ,  Je-Hsiung Lan ,  Robert P. Mikulka ,  Matthew M. Nowak

IPC: H03H7/46 ,  H03H3/00

CPC classification number: H03H7/463 ,  H03H3/00 ,  Y10T29/4902

Abstract: Systems for reducing magnetic coupling in integrated circuits (ICs) are disclosed. Related components and methods are also disclosed. The ICs have a plurality of inductors. Each inductor generates a magnetic flux that has a discernible axis. To reduce magnetic coupling between the inductors, the flux axes are designed so as to be non-parallel. In particular, by making the flux axes of the inductors non-parallel to one another, magnetic coupling between the inductors is reduced relative to the situation where the flux axes are parallel. This arrangement may be particularly well suited for use in diplexers having a low pass and a high pass filter.

Abstract translation: 公开了用于减小集成电路（IC）中的磁耦合的系统。 还公开了相关的部件和方法。 IC具有多个电感器。 每个电感器产生具有可辨别轴线的磁通量。 为了减小电感器之间的磁耦合，磁通轴被设计成不平行。 特别地，通过使电感器的磁通轴彼此不平行，相对于磁通轴平行的情况，电感器之间的磁耦合减小。 这种布置可以特别适用于具有低通和高通滤波器的双工器。

公开(公告)号：US20140327508A1

公开(公告)日：2014-11-06

申请号：US13887633

申请日：2013-05-06

Applicant: QUALCOMM INCORPORATED

Inventor： Daeik D. Kim ,  Kangho Lee ,  David F. Berdy ,  Mario Francisco Velez ,  Jonghae Kim ,  Je-Hsiung Lan ,  Changhan Yun ,  Niranjan Sunil Mudakatte ,  Robert P. Mikulka

IPC: H01F29/14

CPC classification number: H01F21/06 ,  H01F21/08 ,  H01F27/255

Abstract: An inductor tunable by a variable magnetic flux density component is disclosed. A particular device includes an inductor. The device further includes a variable magnetic flux density component (VMFDC) positioned to influence a magnetic field of the inductor when a current is applied to the inductor.

Abstract translation: 公开了一种由可变磁通密度分量调节的电感器。 特定器件包括电感器。 该装置还包括可变磁通密度分量（VMFDC），其定位成当电流施加到电感器时影响电感器的磁场。

公开(公告)号：US20140197902A1

公开(公告)日：2014-07-17

申请号：US13798733

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Chengjie Zuo ,  Jonghae Kim ,  Mario Francisco Velez ,  Je-Hsiung Lan ,  Daeik D. Kim ,  Changhan Yun ,  David F. Berdy ,  Robert P. Mikulka ,  Matthew M. Nowak ,  Xiangdong Zhang ,  Puay H. See

IPC: H03H7/46 ,  H03H3/00

CPC classification number: H03H7/461 ,  H01F2017/0026 ,  H01F2017/004 ,  H01L23/15 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/64 ,  H01L23/66 ,  H01L2924/0002 ,  H03H3/00 ,  H03H7/1758 ,  H03H7/1766 ,  H03H7/1791 ,  H03H7/463 ,  H03H2001/0021 ,  H05K1/0233 ,  H05K1/0306 ,  H05K1/165 ,  H05K2201/09627 ,  H05K2201/09672 ,  H05K2201/10015 ,  H05K2201/10098 ,  Y10T29/49128 ,  H01L2924/00

Abstract: A diplexer includes a substrate having a set of through substrate vias. The diplexer also includes a first set of traces on a first surface of the substrate. The first traces are coupled to the through substrate vias. The diplexer further includes a second set of traces on a second surface of the substrate that is opposite the first surface. The second traces are coupled to opposite ends of the set of through substrate vias. The through substrate vias and the traces also operate as a 3D inductor. The diplexer also includes a capacitor supported by the substrate.

Abstract translation: 双工器包括具有一组通过衬底通孔的衬底。 双工器还包括在衬底的第一表面上的第一组迹线。 第一迹线耦合到贯穿衬底通孔。 双工器还包括与第一表面相对的在衬底的第二表面上的第二组迹线。 第二迹线耦合到该组通过衬底通孔的相对端。 贯通衬底通孔和迹线也作为3D电感器工作。 双工器还包括由基板支撑的电容器。

公开(公告)号：US09813043B2

公开(公告)日：2017-11-07

申请号：US15079789

申请日：2016-03-24

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Daeik D. Kim ,  Je-Hsiung Lan ,  Jonghae Kim ,  Mario Francisco Velez ,  Changhan Yun ,  David F. Berdy ,  Robert P. Mikulka ,  Matthew M. Nowak ,  Xiangdong Zhang ,  Puay H. See

IPC: H03H7/46 ,  H03H3/00 ,  H03H7/01

CPC classification number: H03H7/461 ,  H03H3/00 ,  H03H7/0115 ,  H03H7/463 ,  Y10T29/49016

Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.

公开(公告)号：US09140747B2

公开(公告)日：2015-09-22

申请号：US13947144

申请日：2013-07-22

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Taehyun Kim ,  Sungryul Kim ,  Daeik D. Kim

IPC: G11C7/00 ,  G01R31/28 ,  G11C29/14 ,  G11C29/44 ,  G11C29/46 ,  G11C16/28 ,  G11C29/02

CPC classification number: G01R31/2851 ,  G11C16/28 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C29/14 ,  G11C29/44 ,  G11C29/46

Abstract: A circuit includes a plurality of transistors responsive to a plurality of latches that store a test code. The circuit further includes a first bit line coupled to a data cell and coupled to a sense amplifier. The circuit also includes a second bit line coupled to a reference cell and coupled to the sense amplifier. A current from a set of the plurality of transistors is applied to the data cell via the first bit line. The set of the plurality of transistors is determined based on the test code. The circuit also includes a test mode reference circuit coupled to the first bit line and to the second bit line.

Abstract translation: 电路包括响应于存储测试码的多个锁存器的多个晶体管。 电路还包括耦合到数据单元并耦合到读出放大器的第一位线。 电路还包括耦合到参考单元并耦合到读出放大器的第二位线。 来自一组多个晶体管的电流经由第一位线被施加到数据单元。 基于测试代码来确定多个晶体管的集合。 电路还包括耦合到第一位线和第二位线的测试模式参考电路。