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    Metal-semiconductor wafer bonding for high-Q devices
    6.
    发明授权
    Metal-semiconductor wafer bonding for high-Q devices 有权
    用于高Q器件的金属半导体晶片接合

    公开(公告)号：US09431510B2

    公开(公告)日：2016-08-30

    申请号：US14554718

    申请日：2014-11-26

    Applicant: QUALCOMM Incorporated

    Inventor： Changhan Yun ,  Chengjie Zuo ,  Chi Shun Lo ,  Jonghae Kim ,  Mario F. Velez

    IPC: H01L21/20 ,  H01L29/66 ,  H01G4/33 ,  H01L49/02 ,  H01G4/12

    CPC classification number: H01L29/66174 ,  H01G4/1272 ,  H01G4/33 ,  H01L28/40 ,  H01L28/75

    Abstract: Methods and apparatus for metal semiconductor wafer bonding for high-Q devices are provided. An exemplary capacitor includes a first plate formed on a glass substrate, a second plate, and a dielectric layer. No organic bonding agent is used between the first plate and the glass substrate, and the dielectric layer can be an intrinsic semiconductor. A extrinsic semiconductor layer that is heavily doped contacts the dielectric layer. The dielectric and extrinsic semiconductor layers are sandwiched between the first and second plates. An intermetallic layer is formed between the first plate and the dielectric layer. The intermetallic layer is thermo compression bonded to the first plate and the dielectric layer. The capacitor can be coupled in a circuit as a high-Q capacitor and/or a varactor, and can be integrated with a mobile device.

    Abstract translation: 提供了用于高Q装置的金属半导体晶片接合的方法和装置。 示例性电容器包括形成在玻璃基板，第二板和介电层上的第一板。 在第一板和玻璃基板之间不使用有机粘合剂，并且电介质层可以是本征半导体。 重掺杂的非本征半导体层接触电介质层。 电介质和非本征半导体层夹在第一和第二板之间。 在第一板和电介质层之间形成金属间层。 金属间化合物层被热压接合到第一板和电介质层。 电容器可以作为高Q电容器和/或变容二极管耦合在电路中，并且可以与移动设备集成。

    THERMAL DESIGN AND ELECTRICAL ROUTING FOR MULTIPLE STACKED PACKAGES USING THROUGH VIA INSERT (TVI)
    7.
    发明申请
    THERMAL DESIGN AND ELECTRICAL ROUTING FOR MULTIPLE STACKED PACKAGES USING THROUGH VIA INSERT (TVI) 有权
    使用通过插入（TVI）的多个堆叠包的热设计和电气路由

    公开(公告)号：US20140252645A1

    公开(公告)日：2014-09-11

    申请号：US13787476

    申请日：2013-03-06

    Applicant: QUALCOMM INCORPORATED

    Inventor： Dong Wook Kim ,  Victor A. Chiriac ,  Kyu-Pyung Hwang ,  Changhan Yun ,  Young K. Song

    IPC: H01L23/34

    CPC classification number: H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

    Abstract: Some implementations provide a semiconductor package structure that includes a package substrate, a first package, an interposer coupled to the first package, and a first set of through via insert (TVI). The first set of TVI is coupled to the interposer and the package substrate. The first set of TVI is configured to provide heat dissipation from the first package. In some implementations, the semiconductor package structure further includes a heat spreader coupled to the interposer. The heat spreader is configured to dissipate heat from the first package. In some implementations, the first set of TVI is further configured to provide an electrical path between the first package and the package substrate. In some implementations, the first package is electrically coupled to the package substrate through the interposer and the first set of TVI. In some implementations, the first set of TVI includes a dielectric layer and a metal layer.

    Abstract translation: 一些实施方案提供半导体封装结构，其包括封装衬底，第一封装，耦合到第一封装的插入器和第一组通孔插入件（TVI）。 第一组TVI耦合到插入器和封装衬底。 第一组TVI配置为提供第一包装散热。 在一些实施方案中，半导体封装结构还包括耦合到插入件的散热器。 散热器被配置为从第一包装散发热量。 在一些实施方式中，第一组TVI被进一步配置成在第一封装和封装衬底之间提供电路径。 在一些实施方案中，第一封装通过插入器和第一组TVI电耦合到封装衬底。 在一些实施方案中，第一组TVI包括电介质层和金属层。

    Backside drill embedded die substrate
    8.
    发明授权
    Backside drill embedded die substrate 有权

    公开(公告)号：US10325855B2

    公开(公告)日：2019-06-18

    申请号：US15074750

    申请日：2016-03-18

    Applicant: QUALCOMM Incorporated

    Inventor： Daeik Kim ,  Jie Fu ,  Changhan Yun ,  Chin-Kwan Kim ,  Manuel Aldrete ,  Chengjie Zuo ,  Mario Velez ,  Jonghae Kim

    IPC: H01L23/538 ,  H01L21/48 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00

    Abstract: A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.

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