公开(公告)号：US10854604B1

公开(公告)日：2020-12-01

申请号：US16578101

申请日：2019-09-20

Applicant: QUALCOMM Incorporated

Inventor： ChihWei Kuo ,  Haining Yang ,  Jun Yuan ,  Kern Rim

IPC: H01L27/092 ,  H03K19/0185 ,  H02M7/515

Abstract: Offsetting or modulating the location of a gate between two transistors may achieve a lower power circuit and a higher speed circuit depending on the new location of the gate. In one example, a gate between a PFET transistor and an NFET transistor may be offset towards the PFET transistor to achieve a higher speed circuit than a conventional circuit with the gate located equal distance between the transistors. In another example, a gate between a PFET transistor and an NFET transistor may be offset towards the NFET transistor to achieve a lower power circuit than a conventional circuit with the gate located equal distance between the transistors.

公开(公告)号：US10134734B2

公开(公告)日：2018-11-20

申请号：US15197949

申请日：2016-06-30

Applicant: QUALCOMM Incorporated

Inventor： Jun Yuan ,  Yanxiang Liu ,  Kern Rim

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/28 ,  H01L29/49

Abstract: Fin Field Effect Transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits with single and double diffusion breaks for increased performance are disclosed. In one aspect, a FinFET CMOS circuit employing single and double diffusion breaks includes a P-type FinFET that includes a first Fin formed from a semiconductor substrate and corresponding to a P-type diffusion region. The FinFET CMOS circuit includes an N-type FinFET that includes a second Fin formed from the semiconductor substrate and corresponding to an N-type diffusion region. To electrically isolate the P-type FinFET, first and second single diffusion break (SDB) isolation structures are formed in the first Fin on either side of a gate of the P-type FinFET. To electrically isolate the N-type FinFET, first and second double diffusion break (DDB) isolation structures are formed in the second Fin on either side of a gate of the N-type FinFET.

公开(公告)号：US09876123B2

公开(公告)日：2018-01-23

申请号：US14495507

申请日：2014-09-24

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Xiao Lu ,  Bin Yang ,  Jun Yuan ,  Xiaonan Chen ,  Zhongze Wang

IPC: G11C16/10 ,  H01L29/792 ,  H01L29/423 ,  H01L29/51 ,  G11C17/18 ,  H01L27/112 ,  G11C16/26 ,  G11C16/04

CPC classification number: H01L29/792 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/26 ,  G11C17/18 ,  H01L27/11206 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517

Abstract: An apparatus includes a metal gate, a substrate material, and an oxide layer between the metal gate and the substrate material. The oxide layer includes a hafnium oxide layer contacting the metal gate and a silicon dioxide layer contacting the substrate material and contacting the hafnium oxide layer. The metal gate, the substrate material, and the oxide layer are included in a one-time programmable (OTP) memory device. The OTP memory device includes a transistor. A non-volatile state of the OTP memory device is based on a threshold voltage shift of the OTP memory device.

公开(公告)号：US20160218211A1

公开(公告)日：2016-07-28

申请号：US14604544

申请日：2015-01-23

Applicant: QUALCOMM Incorporated

Inventor： Jun Yuan ,  Xia Li ,  Bin Yang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49 ,  H01L21/02 ,  H01L29/161 ,  H01L29/51

CPC classification number: H01L29/7827 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/161 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66356 ,  H01L29/66666 ,  H01L29/66977 ,  H01L29/7391

Abstract: In a particular embodiment, an apparatus includes an electron tunnel structure. The electron tunnel structure includes a tunneling layer, a channel layer, a source layer, and a drain layer. The tunneling layer and the channel layer are positioned between the source layer and the drain layer. The transistor device further includes a high-k dielectric layer adjacent to the electron tunnel structure.

Abstract translation: 在特定实施例中，一种装置包括电子隧道结构。 电子隧道结构包括隧道层，沟道层，源极层和漏极层。 隧道层和沟道层位于源极层和漏极层之间。 晶体管器件还包括与电子隧道结构相邻的高k电介质层。

公开(公告)号：US20160020220A1

公开(公告)日：2016-01-21

申请号：US14495507

申请日：2014-09-24

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Xiao Lu ,  Bin Yang ,  Jun Yuan ,  Xiaonan Chen ,  Zhongze Wang

IPC: H01L27/115 ,  G11C16/10 ,  G11C16/26 ,  H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/26 ,  G11C17/18 ,  H01L27/11206 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517

Abstract: An apparatus includes a metal gate, a substrate material, and an oxide layer between the metal gate and the substrate material. The oxide layer includes a hafnium oxide layer contacting the metal gate and a silicon dioxide layer contacting the substrate material and contacting the hafnium oxide layer. The metal gate, the substrate material, and the oxide layer are included in a one-time programmable (OTP) memory device. The OTP memory device includes a transistor. A non-volatile state of the OTP memory device is based on a threshold voltage shift of the OTP memory device.

Abstract translation: 一种装置包括金属栅极，衬底材料和金属栅极和衬底材料之间的氧化物层。 氧化物层包括与金属栅极接触的氧化铪层和与衬底材料接触并与氧化铪层接触的二氧化硅层。 金属栅极，衬底材料和氧化物层包括在一次性可编程（OTP）存储器件中。 OTP存储器件包括晶体管。 OTP存储器件的非易失性状态基于OTP存储器件的阈值电压偏移。

公开(公告)号：US20240413219A1

公开(公告)日：2024-12-12

申请号：US18333004

申请日：2023-06-12

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Jun Yuan

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Forces applied to the channel regions of semiconductor slabs in a first direction relative to the semiconductor slab, can create strains in the crystal structure that improve carrier mobility to improve drive strength in the channel region. In a three-dimensional (3D) FET structure, a work function metal layer is provided on opposing faces of semiconductor slabs to cause a force to be exerted on the channel regions in a first direction corresponding to current flow. The force in the first direction is either tensile force or compressive force, depending on a FET type (N or P) employing the semiconductor slab, and is provided to create strain in a crystalline structure of the semiconductor slab to improve carrier mobility in the channel region. Increasing carrier mobility in the channel regions in a 3D FET structure increases drive strength of the 3D FET, which saves area in an integrated circuit.

公开(公告)号：US20190195700A1

公开(公告)日：2019-06-27

申请号：US16268669

申请日：2019-02-06

Applicant: QUALCOMM Incorporated

Inventor： Lixin Ge ,  Periannan Chidambaram ,  Bin Yang ,  Jiefeng Jeff Lin ,  Giridhar Nallapati ,  Bo Yu ,  Jie Deng ,  Jun Yuan ,  Stanley Seungchul Song

IPC: G01K7/01 ,  H01L23/522 ,  H01L23/34 ,  G01K7/18 ,  H01L49/02 ,  G01K7/24 ,  H01L21/768 ,  H01L21/3213 ,  H01L23/528 ,  H01L21/66

CPC classification number: G01K7/01 ,  G01K7/186 ,  G01K7/24 ,  H01L21/32139 ,  H01L21/76895 ,  H01L22/34 ,  H01L23/34 ,  H01L23/5228 ,  H01L23/528 ,  H01L27/0629 ,  H01L28/24

Abstract: Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC adjacent to an active semiconductor area to sense ambient temperature in the adjacent active semiconductor area. Voltage of the metal resistor will change as a function of ambient temperature of the metal resistor, which can be sensed to measure the ambient temperature around devices in the active semiconductor layer adjacent to the metal resistor. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized adjacent and close to semiconductor devices to more accurately sense ambient temperature of the semiconductor devices. The same fabrication processes used to create contacts in the MOL layer can be used to fabricate the metal resistor.

公开(公告)号：US09997360B2

公开(公告)日：2018-06-12

申请号：US15271867

申请日：2016-09-21

Applicant: QUALCOMM Incorporated

Inventor： Da Yang ,  Yanxiang Liu ,  Jun Yuan ,  Kern Rim

IPC: H01L29/76 ,  H01L21/28 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3213

CPC classification number: H01L21/28123 ,  H01L21/32139 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.

公开(公告)号：US20180058943A1

公开(公告)日：2018-03-01

申请号：US15246006

申请日：2016-08-24

Applicant: QUALCOMM Incorporated

Inventor： Lixin Ge ,  Chidi Chidambaram ,  Bin Yang ,  Jiefeng Jeff Lin ,  Giridhar Nallapati ,  Bo Yu ,  Jie Deng ,  Jun Yuan ,  Stanley Seungchul Song

IPC: G01K7/01 ,  H01L21/66 ,  H01L49/02 ,  H01L23/528 ,  H01L21/3213 ,  H01L21/768 ,  G01K7/24

CPC classification number: G01K7/01 ,  G01K7/186 ,  G01K7/24 ,  H01L21/32139 ,  H01L21/76895 ,  H01L22/34 ,  H01L23/34 ,  H01L23/5228 ,  H01L23/528 ,  H01L27/0629 ,  H01L28/24

Abstract: Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC adjacent to an active semiconductor area to sense ambient temperature in the adjacent active semiconductor area. Voltage of the metal resistor will change as a function of ambient temperature of the metal resistor, which can be sensed to measure the ambient temperature around devices in the active semiconductor layer adjacent to the metal resistor. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized adjacent and close to semiconductor devices to more accurately sense ambient temperature of the semiconductor devices. The same fabrication processes used to create contacts in the MOL layer can be used to fabricate the metal resistor.

公开(公告)号：US09570442B1

公开(公告)日：2017-02-14

申请号：US15133832

申请日：2016-04-20

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang Liu ,  Jun Yuan

IPC: H01L21/00 ,  H01L27/088 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649

Abstract: Aspects for applying channel stress to Fin field-effect transistors (FETs) (FinFETs) using a self-aligned single diffusion break (SDB) isolation structure are disclosed. In one aspect, a FinFET-based circuit is provided. The FinFET-based circuit includes a semiconductor substrate and a Fin formed from the semiconductor substrate. The FinFET-based circuit also includes first and second FinFETs, each corresponding to the Fin. The FinFET-based circuit also includes a gate region disposed between the first FinFET and the second FinFET. An SDB isolation structure is formed in the Fin between the first FinFET and the second FinFET. The self-aligned SDB isolation structure is self-aligned with the gate region and electrically isolates the first FinFET and the second FinFET. The self-aligned SDB isolation structure applies stress to a first channel corresponding to the first FinFET and to a second channel corresponding to the second FinFET.

Abstract translation: 公开了使用自对准单扩散断裂（SDB）隔离结构将沟道应力施加到鳍状场效应晶体管（FET）（FinFET）的方面。 在一个方面，提供了基于FinFET的电路。 基于FinFET的电路包括半导体衬底和由半导体衬底形成的鳍。 基于FinFET的电路还包括第一和第二FinFET，每个FinFET对应于Fin。 基于FinFET的电路还包括设置在第一FinFET和第二FinFET之间的栅极区域。 在第一FinFET和第二FinFET之间的Fin中形成SDB隔离结构。 自对准SDB隔离结构与栅极区域自对准并且电隔离第一FinFET和第二FinFET。 自对准SDB隔离结构将应力施加到对应于第一FinFET的第一通道和对应于第二FinFET的第二通道。