公开(公告)号：US20240347913A1

公开(公告)日：2024-10-17

申请号：US18300067

申请日：2023-04-13

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta ,  Jonghae Kim ,  Je-Hsiung Lan

IPC: H01Q9/04 ,  H01Q1/22

CPC classification number: H01Q9/0407 ,  H01Q1/2283

Abstract: An antenna module as a radio-frequency (RF) integrated circuit (IC) semiconductor die (“die”) with an integrated antenna substrate. The die with the integrated antenna substrate can be provided as part of a single IC chip that is fabricated as part of a wafer-level fabrication process as an example. The antenna elements are formed in one more antenna layers as part of an antenna substrate. The antenna layers may be formed as re-distribution layers (RDLs) for example to support smaller line-spacing (LS) and/or smaller pitched metal interconnects for forming and interconnecting to smaller wavelength antenna elements for supporting higher frequency communications. The antenna substrate is formed on a semiconductor wafer of an IC as part of the die. In this manner, the antenna layers can be formed as part of a wafer-level fabrication process used to form the die to form the antenna layers.

公开(公告)号：US12046530B2

公开(公告)日：2024-07-23

申请号：US17558508

申请日：2021-12-21

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Lan ,  Jonghae Kim ,  Ranadeep Dutta

IPC: H01L21/48 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/3677 ,  H01L21/4871 ,  H01L25/0655 ,  H01L25/50

Abstract: Disclosed are apparatuses and techniques for fabricating an apparatus including a semiconductor device. The semiconductor device may include: a die, a thermally conductive interface that includes a thermal bridge interposer (THBI) structure, and a substrate. The die is coupled to the substrate by the thermally conductive interface and at least a portion of the die is coupled to the substrate by the THBI structure.

公开(公告)号：US20230268637A1

公开(公告)日：2023-08-24

申请号：US17652328

申请日：2022-02-24

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta ,  Jonghae Kim ,  Je-Hsiung Lan

IPC: H01Q1/22 ,  H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01L23/66 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01Q1/2283 ,  H01L23/3672 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/20 ,  H01L25/105 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L24/19 ,  H01L25/50 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L2225/1094

Abstract: Antenna modules employing three-dimensional (3D) build-up on mold package to support efficient integration of radio-frequency (RF) circuitry, and related fabrication methods. The antenna module includes a RF transceiver whose circuitry is split over multiple semiconductor dies (“dies”) so different semiconductor devices can be formed in different semiconductor structures. The antenna module is provided as a 3D build-up on mold package to reduce lengths of die-to-die (D2D) interconnections between circuits in different dies. First and second die packages that include respective first and second dies encapsulated in respective first and second mold layers are coupled to each other in a vertical direction in a 3D stacked arrangement with active faces of the first and second dies facing each other to provide a reduced distance between the active faces of the first and second dies. An antenna is stacked on the second die package to provide an antenna(s) for the antenna module.

公开(公告)号：US11355617B2

公开(公告)日：2022-06-07

申请号：US16589444

申请日：2019-10-01

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta ,  Stephen Alan Fanelli ,  Richard Hammond

IPC: H01L29/66 ,  H01L29/737 ,  H01L29/08

Abstract: Certain aspects of the present disclosure generally relate to an integrated circuit (IC) having a heterojunction bipolar transistor (HBT) device. The HBT device generally includes an emitter region, a collector region, and a base region disposed between the emitter region and the collector region, the base region and the collector region comprising different semiconductor materials. The HBT device may also include an etch stop layer disposed between the collector region and the base region. The HBT device also includes an emitter contact, wherein the emitter region is between the emitter contact and the base region, and a collector contact, wherein the collector region is between the collector contact and the base region.

公开(公告)号：US10748891B1

公开(公告)日：2020-08-18

申请号：US16274129

申请日：2019-02-12

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: A multi-gate active device includes a source region coupled to source contacts and a first drain region coupled to first drain contacts. The multi-gate active device also includes a first meshed silicide stop on the first drain region. The first meshed silicide stop surrounds the first drain contacts. The multi-gate active device further includes a first gate over a first channel between the source region and the first drain region.

公开(公告)号：US10707352B2

公开(公告)日：2020-07-07

申请号：US16149505

申请日：2018-10-02

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta

IPC: H01L29/786 ,  H01L29/66

Abstract: Certain aspects of the present disclosure generally relate to a transistor having an implant region for reducing a net doping concentration below an edge of a gate region of the transistor. One example transistor generally includes a first semiconductor region, a second semiconductor region, and a third semiconductor region, the first semiconductor region being between and having a different doping type than the second semiconductor region and the third semiconductor region. In certain aspects, the transistor also includes a gate dielectric layer disposed above the first semiconductor region, a non-insulative region disposed above the gate dielectric layer, and an implant region disposed above the second semiconductor region, the implant region having a different doping type than the second semiconductor region.

公开(公告)号：US20150035072A1

公开(公告)日：2015-02-05

申请号：US13958646

申请日：2013-08-05

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta ,  Choh Fei Yeap

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/82385 ,  H01L21/823857 ,  H01L23/66 ,  H01L27/0207 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/7833 ,  H01L2924/0002 ,  H03F1/0277 ,  H03F3/195 ,  H03F3/245 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/429 ,  H03F2200/432 ,  H03F2203/7209 ,  H03F2203/7236 ,  H01L2924/00

Abstract: A method includes forming a first gate oxide in a first region and in a second region of a wafer. The method further includes performing first processing to form a second gate oxide in the second region. The second gate oxide has a different thickness than the first gate oxide. The method also includes forming first gate material of a first device in the first region and forming second gate material of a second device in the second region. The first device corresponds to a first radio frequency (RF) band and the second device corresponds to a second RF band that is different from the first RF band.

Abstract translation: 一种方法包括在晶片的第一区域和第二区域中形成第一栅极氧化物。 该方法还包括执行第一处理以在第二区域中形成第二栅极氧化物。 第二栅极氧化物具有与第一栅极氧化物不同的厚度。 该方法还包括在第一区域中形成第一器件的第一栅极材料并在第二区域中形成第二器件的第二栅极材料。 第一设备对应于第一射频（RF）频带，第二设备对应于与第一RF频带不同的第二RF频段。

公开(公告)号：US11984874B2

公开(公告)日：2024-05-14

申请号：US17409282

申请日：2021-08-23

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta ,  Jonghae Kim ,  Je-Hsiung Lan

IPC: H03H9/64 ,  H03H3/10 ,  H03H9/02 ,  H03H9/05 ,  H03H9/10

CPC classification number: H03H9/6406 ,  H03H3/10 ,  H03H9/02834 ,  H03H9/059 ,  H03H9/1071

Abstract: Surface acoustic wave (SAW) filter packages employing an enhanced thermally conductive cavity frame for heat dissipation, and related fabrication methods are disclosed. The SAW filter package also includes a cavity frame comprising a perimeter structure and a cavity inside the perimeter structure coupled to a substrate of a piezoelectric material that contains interdigital transducers (IDTs). A cap substrate is disposed on the perimeter structure of the cavity frame to enclose an air cavity inside the perimeter structure between a substrate and the cap substrate. In exemplary aspects, to effectively dissipate heat generated in the SAW filter package to maintain the desired performance of the SAW filter, the cavity frame is comprised of a material that has an enhanced thermal conductivity. The heat generated in the SAW filter package can more effectively be dissipated, particularly at edges and corners of the cavity frame where hot spots can particularly occur.

公开(公告)号：US11862367B2

公开(公告)日：2024-01-02

申请号：US17643685

申请日：2021-12-10

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Sang-June Park ,  Je-Hsiung Lan ,  Ranadeep Dutta

IPC: H01C7/00

CPC classification number: H01C7/006

Abstract: Disclosed is a sheet resistor designed to operate in a high frequency environment. Unlike conventional sheet resistors, the equivalent series inductance (ESL) is minimized or even eliminated altogether when using the designed sheet resistor. As a result, better signal isolation can be achieved.

公开(公告)号：US11749746B2

公开(公告)日：2023-09-05

申请号：US17244293

申请日：2021-04-29

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta ,  Jonghae Kim ,  Je-Hsiung Lan

IPC: H01L29/737 ,  H01L23/14 ,  H01L23/498 ,  H01L23/00 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/7371 ,  H01L23/147 ,  H01L23/49844 ,  H01L24/08 ,  H01L24/80 ,  H01L29/205 ,  H01L29/66318 ,  H01L2224/08165 ,  H01L2224/80001

Abstract: In an aspect, a heterojunction bipolar transistor (HBT) includes a sub-collector disposed on a collector. The collector has a collector contact disposed on the sub-collector and located on a first side of the heterojunction bipolar transistor. The HBT includes an emitter disposed on an emitter cap. The emitter has an emitter contact disposed on the emitter cap and located on a second side of the heterojunction bipolar transistor. The HBT includes a base having a base contact located on the second side of the heterojunction bipolar transistor.