公开(公告)号：US09875776B1

公开(公告)日：2018-01-23

申请号：US15363401

申请日：2016-11-29

Applicant: QUALCOMM Incorporated

Inventor： Priyankar Mathuria ,  Rakesh Kumar Sinha ,  Sharad Kumar Gupta

IPC: G11C7/00 ,  G11C7/12 ,  G11C7/10

CPC classification number: G11C7/1009 ,  G11C7/1084 ,  G11C2207/2227

Abstract: Maskable level shifter circuits and memories are provided. Memories may include a plurality of memory cells and a bitline coupled to the plurality of memory cells. The memories includes a maskable level shifter configured to receive write data and a mask signal. A maskable level shifter includes a level shifter configured to level shift the write data and output the level shifted write data to the bitline when the mask signal is inactive and a masking circuit configured to remove power from the level shifter when the mask signal is active. Another maskable level shifter includes a level shifter configured to level shift the write data and output the level shifted write data to the bitline when the mask signal is inactive and a masking circuit configured to output a predetermined state to the bitline when the mask signal is active.

公开(公告)号：US12183393B2

公开(公告)日：2024-12-31

申请号：US18603118

申请日：2024-03-12

Applicant: QUALCOMM Incorporated

Inventor： Pradeep Raj ,  Rahul Sahu ,  Sharad Kumar Gupta

IPC: G11C11/418 ,  G11C11/419

Abstract: A multi-port memory is provided that supports collision between a read port and a write port to the same multi-port bitcell. A sense amplifier reads a data bit from a multi-port bitcell when a write port to the multi-port bitcell is addressed during a system clock signal. Should a read port to the multi-port bitcell be addressed during the same system clock signal, a multiplexer selects for an output bit from the sense amplifier.

公开(公告)号：US11228312B1

公开(公告)日：2022-01-18

申请号：US16930151

申请日：2020-07-15

Applicant: QUALCOMM Incorporated

Inventor： Narender Ponna ,  Sharad Kumar Gupta ,  Akhtar Alam

IPC: H03K19/003 ,  H03K19/017 ,  H03K19/0185

Abstract: According to certain aspects, a level shifter includes a first branch including a first pull-up transistor configured to pull up a first node, and a first pull-down transistor configured to pull down the first node. The level shifter also includes a second branch including a second pull-up transistor configured to pull up a second node, and a second pull-down transistor configured to pull down the second node. The level shifter further includes a third branch including a third pull-up transistor configured to pull up a third node, and a third pull-down transistor configured to pull down the third node. The first branch is cross coupled with the third branch, the second branch is cross coupled with the third branch, the first pull-down transistor has a first channel width, the second pull-down transistor has a second channel width, and the first channel width is greater than the second channel width.

公开(公告)号：US10140224B2

公开(公告)日：2018-11-27

申请号：US15461184

申请日：2017-03-16

Applicant: QUALCOMM Incorporated

Inventor： Mukund Narasimhan ,  Sharad Kumar Gupta ,  Dharaneedharan Shanmugasundaram

IPC: G11C11/00 ,  G06F13/16 ,  G11C7/10 ,  G11C11/418 ,  G11C11/419 ,  G11C7/02 ,  G11C7/12

Abstract: In an aspect of the disclosure, an apparatus is provided. In one aspect, the apparatus is a memory apparatus. The memory apparatus includes a memory. The memory includes first and second bitcell arrays. The memory apparatus also includes a sense amplifier. The sense amplifier is shared by the first and the second bitcell arrays. Additionally, the sense amplifier is configured to amplify data stored in the memory during a read operation. The memory apparatus also includes a write circuit. The write circuit is configured to write data to the memory during a write operation. The memory apparatus also includes a controller. The controller is configured to disable the write circuit during the read operation.

公开(公告)号：US09947419B1

公开(公告)日：2018-04-17

申请号：US15472121

申请日：2017-03-28

Applicant: QUALCOMM Incorporated

Inventor： Rakesh Kumar Sinha ,  Priyankar Mathuria ,  Sharad Kumar Gupta

IPC: G11C29/50 ,  G11C29/12 ,  G11C11/419

CPC classification number: G11C29/1201 ,  G11C11/419 ,  G11C29/02 ,  G11C29/32 ,  G11C2029/1204 ,  G11C2029/3202

Abstract: A first bitline driver includes a multiplexer for outputting data and write mask signals in functional mode, and test vector signal in test mode; a latch to latch the data signal in functional mode and the test vector signal in test mode; a latch to latch the write mask signal in functional mode and the test vector signal in test mode; a latch to latch the test vector signal and provide it to a scan output; and a write circuit for writing data to a memory cell based on the data signal. A second bitline driver includes a latch to latch a data signal in functional mode if a write mask signal is deasserted and to latch a test vector signal in test mode; a latch to latch the test vector signal and provide it to a scan output; and a write circuit for writing data to a memory cell.

公开(公告)号：US09865316B2

公开(公告)日：2018-01-09

申请号：US15003444

申请日：2016-01-21

Applicant: QUALCOMM Incorporated

Inventor： Sharad Kumar Gupta ,  Mukund Narasimhan ,  Veerabhadra Rao Boda

IPC: G11C7/00 ,  G11C7/22 ,  G11C11/419 ,  G11C11/418 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18

CPC classification number: G11C7/227 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/418 ,  G11C11/419 ,  G11C2207/229

Abstract: A memory is provided in which the word line assertion during a write operation is delayed until the discharge of a dummy bit line is detected.

公开(公告)号：US20170213587A1

公开(公告)日：2017-07-27

申请号：US15003444

申请日：2016-01-21

Applicant: QUALCOMM Incorporated

Inventor： Sharad Kumar Gupta ,  Mukund Narasimhan ,  Veerabhadra Rao Boda

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C7/227 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/418 ,  G11C11/419 ,  G11C2207/229

Abstract: A memory is provided in which the word line assertion during a write operation is delayed until the discharge of a dummy bit line is detected.

公开(公告)号：US09607674B1

公开(公告)日：2017-03-28

申请号：US14989750

申请日：2016-01-06

Applicant: QUALCOMM Incorporated

Inventor： Mukund Narasimhan ,  Sharad Kumar Gupta ,  Veerabhadra Rao Boda

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G06F1/04 ,  G11C5/14 ,  G11C7/02 ,  G11C7/20 ,  H03K3/356173 ,  H03K5/135

Abstract: A method and an apparatus for generating an internal memory clock are provided. The apparatus includes a pulse generator configured to receive a first clock signal in a first power domain and initiate a second clock signal in a second power domain in response to the first clock signal. The first power domain provides a first voltage for logic operations and the second power domain provides a second voltage for memory operations. The apparatus includes a tracking circuit configured to generate a reset signal based on a voltage level of the first power domain. The reset signal may be configured to reset the pulse generator in the first power domain. The apparatus may further include a latch configured to receive the second clock signal in the second power domain.

公开(公告)号：US12047073B2

公开(公告)日：2024-07-23

申请号：US17922176

申请日：2021-04-29

Applicant: QUALCOMM Incorporated

Inventor： Pradeep Raj ,  Rahul Sahu ,  Sharad Kumar Gupta ,  Chulmin Jung

IPC: H03K3/012 ,  H03K5/01 ,  H03K17/56 ,  H03K5/00

CPC classification number: H03K3/012 ,  H03K5/01 ,  H03K17/56 ,  H03K2005/00078

Abstract: Apparatuses and methods to reduce leakage current are presented. The includes a switch circuit configured to power a circuit block; a delay circuit configured to delay enabling the switch circuit powering the circuit block and to be powered down; and a bypass circuit configured to bypass the delay circuit to disable the switch circuit powering the circuit block. The method includes powering, by switch, a circuit block; powering down a delay circuit; and bypassing, by a bypass circuit, the delay circuit to disable the switch circuit powering the circuit block.

公开(公告)号：US12020766B2

公开(公告)日：2024-06-25

申请号：US17654295

申请日：2022-03-10

Applicant: QUALCOMM Incorporated

Inventor： Pradeep Raj ,  Rahul Sahu ,  Sharad Kumar Gupta ,  Hemant Patel ,  Diwakar Singh

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/12

CPC classification number: G11C7/1012 ,  G11C7/06 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/1096 ,  G11C7/12

Abstract: One implementation includes a random access memory (RAM) that has a muted multiplexing functionality. For instance, a RAM may be implemented having a first outer bank, a first inner bank, a second outer bank, and a second inner bank, each coupled to a controller. Multiplexing circuits for the outer banks may be disposed adjacent the outer banks and away from the controller, whereas the multiplexing circuits for the inner banks may be disposed within or adjacent to the controller.