公开(公告)号：US09847293B1

公开(公告)日：2017-12-19

申请号：US15240952

申请日：2016-08-18

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli ,  Plamen Vassilev Kolev ,  Michael Andrew Stuber ,  Richard Hammond ,  Shiqun Gu ,  Steve Fanelli

IPC: H01L21/48 ,  H01L23/528 ,  H01L27/12 ,  H01L29/06 ,  H01L23/522 ,  H01L23/66 ,  H01L23/532 ,  H01L49/02 ,  H04B1/16

CPC classification number: H01L23/5283 ,  H01L23/5223 ,  H01L23/53209 ,  H01L23/66 ,  H01L27/1203 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/66181 ,  H01L29/94 ,  H01L2223/6677 ,  H04B1/16

Abstract: An integrated circuit structure may include a capacitor having a semiconductor layer as a first plate and a gate layer as a second plate. A capacitor dielectric layer may separate the first plate and the second plate. A backside metallization may be coupled to the first plate of the capacitor. A front-side metallization may be coupled to the second plate of the capacitor. The front-side metallization may be arranged distal from the backside metallization.

公开(公告)号：US09837302B1

公开(公告)日：2017-12-05

申请号：US15249112

申请日：2016-08-26

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli ,  Stephen Alan Fanelli

IPC: H01L49/02 ,  H01L23/66 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H04W88/00

CPC classification number: H01L21/76256 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0694 ,  H01L27/1203 ,  H04W88/005

Abstract: A method includes performing an etching process from a second side of a buried dielectric layer to expose an etch stop layer, where the second side of the buried dielectric layer is opposite a first side of the buried dielectric layer, and where a first semiconductor device is positioned on the first side of the buried dielectric layer. The method further includes forming a second semiconductor device on the second side of the buried dielectric layer.

公开(公告)号：US11309352B2

公开(公告)日：2022-04-19

申请号：US16116744

申请日：2018-08-29

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli ,  Stephen Alan Fanelli ,  Yun Han Chu

IPC: H01L27/00 ,  H01L27/20 ,  H03H9/05 ,  H03H9/56 ,  H03H3/02 ,  H03H3/08 ,  H03H9/64 ,  H03H3/007 ,  H03H9/10 ,  H03H9/54 ,  H03H9/46 ,  B81C1/00 ,  H03H1/00

Abstract: A radio frequency (RF) front-end (RFFE) device includes a die having a front-side dielectric layer on an active device. The active device is on a first substrate. The RFFE device also includes a microelectromechanical system (MEMS) device. The MEMS device is integrated on the die at a different layer than the active device. The MEMS device includes a cap layer composed of a cavity in the front-side dielectric layer of the die. The cavity in the front-side dielectric layer is between the first substrate and a second substrate. The cap is coupled to the front-side dielectric layer.

公开(公告)号：US10680086B2

公开(公告)日：2020-06-09

申请号：US16011430

申请日：2018-06-18

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli ,  George Pete Imthurn ,  Stephen Alan Fanelli

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/66

Abstract: A heterojunction bipolar transistor is integrated on radio frequency (RF) dies of different sizes. The heterojunction bipolar transistor includes an emitter on a first-side of a semiconductor-on-insulator (SOI) layer of an SOI substrate. The emitter is accessed from the first-side while a collector is accessed from a second-side of the SOI substrate. One or more portions of a base of the heterojunction bipolar transistor is between the emitter and one or more portions of the collector. The heterojunction bipolar transistor also includes a compound semiconductor layer between the collector and the emitter. The compound semiconductor layer carries a charge between the emitter and the collector.

公开(公告)号：US10522626B2

公开(公告)日：2019-12-31

申请号：US15993679

申请日：2018-05-31

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli ,  George Pete Imthurn ,  Yun Han Chu ,  Qingqing Liang

IPC: H01L29/10 ,  H01L27/12 ,  H01L21/285 ,  H01L21/84 ,  H01L21/74 ,  H01L29/45

Abstract: In certain aspects, an apparatus comprises an SOI MOSFET having a diffusion region as a source or a drain on a back insulating layer, wherein the diffusion region has a front diffusion side and a back diffusion side opposite to the front diffusion side; a silicide layer on the front diffusion side having a back silicide side facing the diffusion region and a front silicide side opposite to the back silicide side; and a backside contact connected to the silicide layer, wherein at least a portion of the backside contact is in the back insulating layer.

公开(公告)号：US10439565B2

公开(公告)日：2019-10-08

申请号：US15976710

申请日：2018-05-10

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli

IPC: H03F3/193 ,  H03F3/21 ,  H01L27/088 ,  H04B15/00 ,  H04B1/04 ,  H01L21/84 ,  H01L27/12 ,  H04B1/00 ,  H04B1/525 ,  H03F3/195 ,  H03F3/24 ,  H03F3/68

Abstract: A low noise amplifier (LNA) device includes a first transistor on a semiconductor on insulator (SOI) layer. The first transistor includes a source region, a drain region, and a gate. The LNA device also includes a first-side gate contact coupled to the gate. The LNA device further includes a second-side source contact coupled to the source region. The LNA device also includes a second-side drain contact coupled to the drain region.

公开(公告)号：US10043752B2

公开(公告)日：2018-08-07

申请号：US15245087

申请日：2016-08-23

Applicant: QUALCOMM Incorporated

Inventor： Perry Wyan Lou ,  Sinan Goktepeli

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/45 ,  H01L23/66

Abstract: An integrated circuit device may include a front-side contact coupled to a front-side metallization. The integrated circuit device may further include a backside contact coupled to a backside metallization. The front-side contact may be directly coupled to the backside contact.

公开(公告)号：US09780210B1

公开(公告)日：2017-10-03

申请号：US15234889

申请日：2016-08-11

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli ,  Richard Hammond

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/74 ,  H01L29/06 ,  H01L29/08 ,  H01L23/528 ,  H01L23/66 ,  H01L21/265 ,  H01L21/324 ,  H01L21/285 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H04B1/40

CPC classification number: H01L29/7838 ,  H01L21/2652 ,  H01L21/28518 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/76256 ,  H01L21/76264 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/528 ,  H01L23/66 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66651 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78654 ,  H01L2223/6677 ,  H01L2224/11 ,  H04B1/006 ,  H04B1/40

Abstract: An integrated circuit structure may include a transistor on a front-side semiconductor layer supported by an isolation layer. The transistor is a first source/drain/body region. The integrated circuit structure may also include a raised source/drain/body region coupled to a backside of the first source/drain/body region of the transistor. The transistor is a raised source/drain/body region extending from the backside of the first source/drain/body region toward a backside dielectric layer supporting the isolation layer. The integrated circuit structure may further include a backside metallization coupled to the raised source/drain/body region.

公开(公告)号：US09704738B2

公开(公告)日：2017-07-11

申请号：US14740505

申请日：2015-06-16

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli

IPC: H01L21/762 ,  H01L21/78 ,  H01L21/304 ,  H01L21/306 ,  H01L21/56 ,  H01L23/522 ,  H01L29/06

CPC classification number: H01L21/76256 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/561 ,  H01L21/78 ,  H01L23/5226 ,  H01L29/0649

Abstract: Bonded semiconductor device structures and device structure fabrication processes to obviate the need for SOI wafers in many device fabrication applications are disclosed. In some examples, multiple etch stop layers are formed in situ during fabrication of an active device structure on a bulk semiconductor wafer. The etch stop layers are incorporated into in a layer transfer process to enable very thin high quality active device layers of substantially uniform across-wafer thickness to be separated from bulk semiconductor wafers and bonded to handle wafers. As a result, these examples can produce high-performance and low-power semiconductor devices while avoiding the high cost of SOI wafers.

公开(公告)号：US09647209B2

公开(公告)日：2017-05-09

申请号：US15164540

申请日：2016-05-25

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli ,  Michael A. Stuber

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L45/1206 ,  H01L27/2418 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/065 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/141 ,  H01L45/1608 ,  H01L45/1675

Abstract: Various methods and devices that involve phase change material (PCM) switches are disclosed. An exemplary integrated circuit comprises an active layer with a plurality of field effect transistor (FET) channels for a plurality of FETs. The integrated circuit also comprises an interconnect layer comprising a plurality of conductive interconnects. The plurality of conductive interconnects couple the plurality of field effect transistors. The integrated circuit also comprises an insulator layer covering at least a portion of the interconnect layer. The integrated circuit also comprises a channel of a radio-frequency (RF) PCM switch. The channel of the RF PCM switch is formed on the insulator layer.