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公开(公告)号：US09684325B1
公开(公告)日：2017-06-20
申请号：US15009600
申请日：2016-01-28
Applicant: QUALCOMM Incorporated
Inventor： Todd Morgan Rasmus
CPC classification number: G05F1/575
Abstract: In certain aspects, a method for voltage regulation includes adjusting, using a feedback circuit, a resistance of a first pass element in a direction that reduces a difference between a reference voltage and a feedback voltage, wherein the first pass element is coupled between an input and an output of a voltage regulator, and the feedback voltage is equal to or proportional to a voltage at the output of the voltage regulator. The method also includes adjusting a bias voltage of the feedback circuit in a direction that reduces the difference between the reference voltage and the feedback voltage.
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12.发明申请公开(公告)号：US20170168518A1
公开(公告)日：2017-06-15
申请号：US14970265
申请日：2015-12-15
Applicant: QUALCOMM Incorporated
Inventor： Todd Morgan Rasmus
IPC: G05F3/26
CPC classification number: G05F3/262 , G05F3/225 , G05F3/24 , G05F3/242 , G05F3/245 , G05F3/267 , G05F3/30
Abstract: An apparatus and method for generating a temperature-compensated reference voltage are disclosed. The apparatus generates substantially equal temperature-compensated currents by controlling (through negative feedback) voltages across separate resistors through which the currents flow, respectively. Two of the temperature-compensated currents are formed by combining (e.g., summing) a complementary to absolute temperature (CTAT) current (ICTAT) and a proportional to absolute temperature (PTAT) current (IPTAT). A reference voltage VREF is produced by configuring the other the temperature-compensated current to flow through an output resistor.
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公开(公告)号：US11764733B2
公开(公告)日：2023-09-19
申请号：US17483142
申请日：2021-09-23
Applicant: QUALCOMM Incorporated
Inventor： Shih-Wei Chou , Todd Morgan Rasmus , Ying Duan , Abhay Dixit
CPC classification number: H03F1/0261 , H03F3/19 , H03F3/193 , H04B1/16 , H04L69/323 , H05K1/0246 , H03F2200/451
Abstract: A receiving apparatus includes a terminating network for a three-wire serial bus and a feedback circuit. Each wire of the three-wire serial bus may be coupled through a resistance to a common node of the terminating network. The feedback circuit has a first amplifier circuit having an input coupled to the common node, a comparator that receives an output of the first amplifier circuit as a first input and a reference voltage as a second input, and a second amplifier circuit responsive to an output of the comparator and configured to inject a current through the common node.
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Patent Agency Ranking
公开(公告)号：US11095273B1
公开(公告)日：2021-08-17
申请号：US16940280
申请日：2020-07-27
Applicant: QUALCOMM Incorporated
Inventor： Todd Morgan Rasmus , Li Sun , Dong Ren
Abstract: In certain aspects, a regenerative stage of a sense amplifier includes a first inverter having an input and an output, and a second inverter having an input and an output. The regenerative stage also includes a third inverter having an input, an output coupled to the input of the second inverter, a first supply terminal coupled to a supply rail, and a second supply terminal coupled to the output of the first inverter. The regenerative stage further includes a fourth inverter having an input, an output coupled to the input of the first inverter, a first supply terminal coupled to the supply rail, and a second supply terminal coupled to the output of the second inverter.
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公开(公告)号：US10326417B1
公开(公告)日：2019-06-18
申请号：US15829774
申请日：2017-12-01
Applicant: QUALCOMM Incorporated
Inventor： Todd Morgan Rasmus , Minhan Chen
IPC: H03F3/45
Abstract: A resistor in a pair of resistors is selectively coupled to a current source through a selection switch during the reset phase of a voltage-mode sense amplifier so that one evaluation node for the voltage-mode sense amplifier is discharged from a power supply voltage by an ohmic voltage drop across the selectively-coupled resistor to null an offset for the voltage-mode sense amplifier.
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16.发明授权公开(公告)号：US10243531B1
公开(公告)日：2019-03-26
申请号：US15701072
申请日：2017-09-11
Applicant: QUALCOMM Incorporated
Inventor： Pradeep Thiagarajan , Xiaobin Yuan , Todd Morgan Rasmus
Abstract: A differential signal processing circuit includes a local common mode voltage control circuit for controlling a common mode voltage of an output differential signal generated by the differential signal processing circuit based on an external common mode control current generated by an external common mode voltage control circuit. The differential signal processing circuit, which may be configured as a variable gain amplifier (VGA) or a continuous time linear equalizer (CTLE), includes a pair of load devices, a pair of input transistors, and a pair of current source transistors coupled via separate paths between upper and lower voltage rails. The external control circuit includes a replica circuit including a replica load device, a replica input transistor, and a replica current source transistor. The external control circuit sets the replica common mode voltage to a target using a current, wherein the external common mode control current is based on that current.
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17.发明授权公开(公告)号：US09800218B1
公开(公告)日：2017-10-24
申请号：US15193716
申请日：2016-06-27
Applicant: QUALCOMM Incorporated
Inventor： Todd Morgan Rasmus
CPC classification number: H03F3/45183 , H03F3/45197 , H03F3/45475 , H03F3/45704 , H03F3/45757 , H03F3/45766 , H03F3/45959 , H03F3/45982 , H03F3/45991 , H03F2200/129 , H03F2200/21 , H03F2200/228 , H03F2200/375 , H03F2200/42 , H03F2203/45004 , H03F2203/45042 , H03F2203/45116 , H03F2203/45134 , H03F2203/45138 , H03F2203/45146 , H03F2203/45151 , H03F2203/45152 , H03F2203/45154 , H03F2203/45156 , H03F2203/45192 , H03F2203/45194 , H03F2203/45212 , H03F2203/45221 , H03F2203/45361 , H03F2203/45471 , H03F2203/45538 , H03F2203/45542 , H03F2203/45544 , H03F2203/45588 , H03F2203/45596 , H03G3/30
Abstract: The disclosure relates to an alternating current (AC) coupling circuit including first and second capacitors having first and second input terminals configured to receive an input differential signal and generate an output differential signal at first and second output terminals of the first and second capacitors. The AC coupling circuit further includes a baseline wander correction circuit configured to make the output differential signal resistant to baseline wander due to the input differential signal including one or more time intervals of unbalanced data. The baseline wander correction circuit includes a differential difference amplifier (DDA) having a first differential input configured to receive the input differential signal, a differential output configured to generate a compensation differential signal, and a second differential input configured to receive the compensation differential signal. The compensation differential signal is applied to the output terminals of the first and second capacitors via a pair of resistors, respectively.
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18.发明授权公开(公告)号：US09647618B1
公开(公告)日：2017-05-09
申请号：US15084910
申请日：2016-03-30
Applicant: QUALCOMM Incorporated
Inventor： Xiaobin Yuan , Joseph Natonio , Mangal Prasad , Todd Morgan Rasmus
CPC classification number: H03G3/004 , H03F3/45197 , H03F3/45708 , H03F2200/411 , H03F2200/453 , H03F2200/456 , H03F2200/555 , H03F2203/45154 , H03F2203/45156 , H03F2203/45418 , H03G1/0023 , H03G1/0029 , H03G5/28
Abstract: The disclosure relates to a system and method for controlling a common mode voltage of an output differential signal of a differential signal processing circuit using a replica circuit and feedback control. The differential signal processing circuit includes two load devices, two input transistors, and two current-source transistors coupled in series between voltage rails, respectively. The replica circuit includes replica load device, replica input transistor, and replica current-source transistor coupled in series between the voltage rails. The common mode voltage of the input differential signal is applied to the replica input transistor to generate a replica output common mode voltage. A feedback circuit generates a bias voltage for the replica current-source transistor and the current-source transistors of the differential circuit to set and control the replica output common mode voltage and the output common mode voltage of the differential signal processing circuit to a target common mode voltage.
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