公开(公告)号：US09524765B2

公开(公告)日：2016-12-20

申请号：US14460626

申请日：2014-08-15

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Seung Hyuk Kang

IPC: G11C11/16 ,  H01L27/22 ,  G11C7/24

CPC classification number: G11C11/1673 ,  G11C7/24 ,  G11C11/16 ,  G11C11/161 ,  G11C11/165 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1695 ,  G11C2213/78 ,  H01L27/228

Abstract: An apparatus includes a first magnetic tunnel junction (MTJ) device of a differential MTJ pair. The apparatus further includes a second MTJ device of the differential MTJ pair. The first MTJ device includes a sense layer having a high coercivity portion.

Abstract translation: 一种装置包括差分MTJ对的第一磁隧道结（MTJ）装置。 该装置还包括差分MTJ对的第二MTJ装置。 第一MTJ装置包括具有高矫顽力部分的感测层。

公开(公告)号：US09508439B2

公开(公告)日：2016-11-29

申请号：US14602090

申请日：2015-01-21

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Xiao Lu ,  Matthew Michael Nowak ,  Seung Hyuk Kang ,  Xiaonan Chen ,  Zhongze Wang ,  Yu Lu

IPC: G11C16/10 ,  H01L29/423 ,  H01L29/792 ,  H01L29/51 ,  G11C16/26 ,  H01L27/112

CPC classification number: G11C16/10 ,  G11C11/223 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C16/26 ,  H01L27/11246 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7836 ,  H01L29/792

Abstract: An apparatus includes a multiple time programmable (MTP) memory device. The MTP memory device includes a metal gate, a substrate material, and an oxide structure between the metal gate and the substrate material. The oxide structure includes a hafnium oxide layer and a silicon dioxide layer. The hafnium oxide layer is in contact with the metal gate and in contact with the silicon dioxide layer. The silicon dioxide layer is in contact with the substrate material. The MTP device includes a transistor, and a non-volatile state of the MTP memory device is based on a threshold voltage of the transistor.

Abstract translation: 一种装置包括多时间可编程（MTP）存储器件。 MTP存储器件包括金属栅极，衬底材料和金属栅极和衬底材料之间的氧化物结构。 氧化物结构包括氧化铪层和二氧化硅层。 氧化铪层与金属栅极接触并与二氧化硅层接触。 二氧化硅层与衬底材料接触。 MTP器件包括晶体管，并且MTP存储器件的非易失性状态基于晶体管的阈值电压。

公开(公告)号：US09343659B1

公开(公告)日：2016-05-17

申请号：US14625494

申请日：2015-02-18

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Wei-Chuan Chen ,  Seung Hyuk Kang

IPC: H01L21/00 ,  H01L43/08 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L27/222 ,  H01L43/02 ,  H01L43/12

Abstract: A magnetoresistive random access memory (MRAM) device includes a top electrode or top contact above a metal hard mask which has a limited height due to process limitations in advanced nodes. The metal hard mask is provided on a magnetic tunnel junction (MTJ). The top contact for the MTJ is formed within a dielectric layer, such as a low dielectric constant (low-k) or extremely low-k layer. An additional dielectric layer is provided above the top contact for additional connections for additional circuitry to form a three-dimensional integrated circuit (3D IC).

Abstract translation: 磁阻随机存取存储器（MRAM）装置包括金属硬掩模上方的顶部电极或顶部触点，由于先进节点中的工艺限制，其具有有限的高度。 金属硬掩模设置在磁性隧道结（MTJ）上。 MTJ的顶部接触形成在介电层内，例如低介电常数（低k）或极低k层。 在顶部触点上方提供了另外的介电层，用于额外的连接，用于附加电路以形成三维集成电路（3D IC）。

公开(公告)号：US09269893B2

公开(公告)日：2016-02-23

申请号：US14243324

申请日：2014-04-02

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Chando Park ,  Wei-Chuan Chen

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L43/02 ,  H01L43/08

Abstract: A multi-step etch technique for fabricating a magnetic tunnel junction (MTJ) apparatus includes forming a first conductive hard mask on a first electrode of the MTJ apparatus for etching the first electrode during a first etching step. The method also includes forming a second conductive hard mask on the first conductive hard mask for etching magnetic layers of the MTJ apparatus during a second etching step. A spacer layer is conformally deposited on sidewalls of the first conductive hard mask. The second conductive hard mask is deposited on the first conductive hard mask and aligned with the spacer layer on the sidewalls of the first conductive hard mask.

Abstract translation: 用于制造磁性隧道结（MTJ）装置的多步骤蚀刻技术包括在第一蚀刻步骤中在MTJ装置的第一电极上形成第一导电硬掩模以蚀刻第一电极。 该方法还包括在第一导电硬掩模上形成第二导电硬掩模，用于在第二蚀刻步骤期间蚀刻MTJ装置的磁性层。 间隔层共形沉积在第一导电硬掩模的侧壁上。 第二导电硬掩模沉积在第一导电硬掩模上并与第一导电硬掩模的侧壁上的间隔层对准。

公开(公告)号：US20160012896A1

公开(公告)日：2016-01-14

申请号：US14602090

申请日：2015-01-21

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Xiao Lu ,  Matthew Michael Nowak ,  Seung Hyuk Kang ,  Xiaonan Chen ,  Zhongze Wang ,  Yu Lu

IPC: G11C16/10 ,  H01L29/423 ,  H01L29/792 ,  G11C16/26 ,  H01L29/51

CPC classification number: G11C16/10 ,  G11C11/223 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C16/26 ,  H01L27/11246 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7836 ,  H01L29/792

Abstract: An apparatus includes a multiple time programmable (MTP) memory device. The MTP memory device includes a metal gate, a substrate material, and an oxide structure between the metal gate and the substrate material. The oxide structure includes a hafnium oxide layer and a silicon dioxide layer. The hafnium oxide layer is in contact with the metal gate and in contact with the silicon dioxide layer. The silicon dioxide layer is in contact with the substrate material. The MTP device includes a transistor, and a non-volatile state of the MTP memory device is based on a threshold voltage of the transistor.

Abstract translation: 一种装置包括多时间可编程（MTP）存储器件。 MTP存储器件包括金属栅极，衬底材料和金属栅极和衬底材料之间的氧化物结构。 氧化物结构包括氧化铪层和二氧化硅层。 氧化铪层与金属栅极接触并与二氧化硅层接触。 二氧化硅层与衬底材料接触。 MTP器件包括晶体管，并且MTP存储器件的非易失性状态基于晶体管的阈值电压。

公开(公告)号：US10008537B2

公开(公告)日：2018-06-26

申请号：US14744984

申请日：2015-06-19

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Xiaochun Zhu ,  Yu Lu

IPC: G11C11/15 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12

CPC classification number: H01L27/226 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A complementary bit cell includes a first magnetic tunnel junction (MTJ) device having a free layer coupled to a first access transistor and having a pinned layer coupled to a bit line. The complementary bit cell also includes a second MTJ device having a free layer coupled to the same bit line and having a pinned layer coupled to a second access transistor.

公开(公告)号：US09728718B2

公开(公告)日：2017-08-08

申请号：US15389322

申请日：2016-12-22

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Matthias Georg Gottwald ,  Mustafa Badaroglu ,  Jimmy Kan ,  Kangho Lee ,  Yu Lu ,  Chando Park

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

Abstract: A semiconductor device includes a first magnetic tunnel junction (MTJ) device, a second MTJ device, and a top electrode. The first MTJ device includes a barrier layer. The second MTJ device includes the barrier layer. The top electrode is coupled to the first MTJ device and the second MTJ device.

公开(公告)号：US09614143B2

公开(公告)日：2017-04-04

申请号：US14735006

申请日：2015-06-09

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Wei-Chuan Chen ,  Seung Hyuk Kang

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L27/22 ,  H01L43/10

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A semiconductor device may include a magnetoresistive random-access memory (MRAM) trench having a first conductive barrier liner and a second conductive barrier liner. The MRAM trench may land on a hard mask of a magnetic tunnel junction (MTJ) within an MTJ region of the semiconductor device. The semiconductor device may also include a logic trench having the first conductive barrier liner. The semiconductor device may further include a logic via having the first conductive barrier liner. The logic via may land on a first portion of a conductive interconnect (Mx) within a logic region of the semiconductor device.

公开(公告)号：US20170047374A1

公开(公告)日：2017-02-16

申请号：US14822326

申请日：2015-08-10

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Seung Hyuk KANG

IPC: H01L27/22 ,  H01L43/02 ,  H01L23/522 ,  G06F17/50 ,  H01L23/528 ,  H01L43/12 ,  H01L43/08

CPC classification number: H01L27/222 ,  G06F17/5045 ,  H01L23/5226 ,  H01L23/528 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A method of fabrication of a device includes forming a first metallization layer that is coupled to a logic device of the device. The method further includes forming a second metallization layer that is coupled to a magnetoresistive random access memory (MRAM) module of the device. The second metallization layer is independent of the first metallization layer.

Abstract translation: 一种制造器件的方法包括形成耦合到器件的逻辑器件的第一金属化层。 该方法还包括形成耦合到该器件的磁阻随机存取存储器（MRAM）模块的第二金属化层。 第二金属化层独立于第一金属化层。

公开(公告)号：US20160372518A1

公开(公告)日：2016-12-22

申请号：US14744984

申请日：2015-06-19

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Xiaochun Zhu ,  Yu Lu

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02

CPC classification number: H01L27/226 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A complementary bit cell includes a first magnetic tunnel junction (MTJ) device having a free layer coupled to a first access transistor and having a pinned layer coupled to a bit line. The complementary bit cell also includes a second MTJ device having a free layer coupled to the same bit line and having a pinned layer coupled to a second access transistor.

Abstract translation: 互补位单元包括具有耦合到第一存取晶体管并具有耦合到位线的被钉扎层的自由层的第一磁隧道结（MTJ）器件。 互补位单元还包括具有耦合到相同位线的自由层并且具有耦合到第二存取晶体管的被钉扎层的第二MTJ器件。