公开(公告)号：US5886398A

公开(公告)日：1999-03-23

申请号：US938360

申请日：1997-09-26

申请人： Qwai H. Low ,  Manickam Thavarajah ,  Chok J. Chia ,  Maniam Alagaratnam

发明人： Qwai H. Low ,  Manickam Thavarajah ,  Chok J. Chia ,  Maniam Alagaratnam

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L23/04 ,  H01L23/28

CPC分类号： H01L23/3128 ,  H01L21/565 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815

摘要： According to the present invention, a semiconductor package is provided. In one version of the invention, the semiconductor package includes a laminated substrate having a semiconductor die mounted on its upper surface, electrical connections between bond pads on the semiconductor die and conductive traces on the substrate, as well as electrical connections between the conductive traces and electrical contacts on the lower surface of the substrate. The semiconductor package also includes a molded covering on the upper surface of the substrate which covers the semiconductor die and the electrical connections. The molded covering has a mold body portion and a mold gate runner which extends from the mold body portion to an edge of the substrate. The mold gate runner is provided with a surface that is substantially even with the edge of the substrate and rises perpendicularly from the upper surface of the substrate.

摘要翻译： 根据本发明，提供一种半导体封装。 在本发明的一个版本中，半导体封装包括具有安装在其上表面上的半导体管芯的层叠衬底，半导体管芯上的焊盘与衬底上的导电迹线之间的电连接以及导电迹线和 在基板的下表面上的电接触。 半导体封装还包括覆盖半导体管芯和电连接的衬底的上表面上的模制覆盖物。 模制的覆盖物具有模具主体部分和模具浇口浇道，模具浇口浇道从模具主体部分延伸到基板的边缘。 模具浇口浇口设置有基本上均匀的衬底的边缘并且从衬底的上表面垂直地上升的表面。

公开(公告)号：US06743979B1

公开(公告)日：2004-06-01

申请号：US10652453

申请日：2003-08-29

申请人： Michael J. Berman ,  Aftab Ahmad ,  Qwai H. Low ,  Chok J. Chia ,  Ramaswamy Ranganathan

发明人： Michael J. Berman ,  Aftab Ahmad ,  Qwai H. Low ,  Chok J. Chia ,  Ramaswamy Ranganathan

IPC分类号： H05K506

CPC分类号： H01L24/06 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/49431 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012

摘要： An integrated circuit, including a substrate with circuitry formed therein, where the substrate has a peripheral edge. Also included are a top most electrically conductive layer and an underlying electrically conductive layer. Outer bonding pads are disposed in an outer ring, and are formed within the top most layer. Inner bonding pads are disposed in an inner ring, and are formed within the top most layer. Inner connectors electrically connect the inner bonding pads to the circuitry. The inner connectors are formed within the underlying layer, and have a width that is less than the width of the inner bonding pads, thereby defining a gap between the inner connectors. Outer connectors electrically connect the outer bonding pads to the circuitry. The outer connectors are formed within the underlying layer, and have a width that is less than the width of the gap between the inner connectors.

摘要翻译： 一种集成电路，包括其中形成有电路的衬底，其中衬底具有外围边缘。 还包括最顶层的导电层和底层导电层。 外部接合焊盘设置在外圈中，并形成在最上层。 内部接合焊盘设置在内圈中，并且形成在最顶层内。 内部连接器将内部接合焊盘电连接到电路。 内部连接器形成在下面的层中，并且具有小于内部焊盘的宽度的宽度，由此限定内部连接器之间的间隙。 外部连接器将外部接合焊盘电连接到电路。 外部连接器形成在下面的层中，并且具有小于内部连接器之间的间隙的宽度的宽度。

公开(公告)号：US06489571B1

公开(公告)日：2002-12-03

申请号：US09703199

申请日：2000-10-31

申请人： Chok J. Chia ,  Qwai H. Low ,  Patrick Variot

发明人： Chok J. Chia ,  Qwai H. Low ,  Patrick Variot

IPC分类号： H05K109

CPC分类号： H01L23/3128 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A molded tape ball grid array package includes a molding compound and a tape substrate having a top surface for mounting a die thereon, a bottom surface for attaching solder balls, and vias for forming connections between the solder balls and the die wherein the molding compound surrounds the die and the tape substrate.

摘要翻译： 模塑带状球栅阵列封装包括模塑料和具有用于在其上安装模具的顶表面的带基材，用于附接焊球的底表面和用于形成焊球和模之间的连接的通孔，其中模塑料围绕 模具和胶带基材。

公开(公告)号：US6143586A

公开(公告)日：2000-11-07

申请号：US97882

申请日：1998-06-15

申请人： Chok J. Chia ,  Patrick Variot ,  Qwai H. Low

发明人： Chok J. Chia ,  Patrick Variot ,  Qwai H. Low

IPC分类号： H01L23/60 ,  H01L21/44 ,  H01L21/331 ,  H01L21/336 ,  H01L21/48 ,  H01L21/50 ,  H01L21/82 ,  H01L31/479

CPC分类号： H01L23/60 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14

摘要： An electrostatic protected integrated circuit (IC) substrate and a method of making an integrated circuit package with the electrostatic protected IC substrate includes an IC substrate, having a plurality of electrical traces formed on the top of the IC substrate with the electrical traces extending from an IC chip mounting area near the center to the periphery of the IC substrate. Electrically shorting the electrical traces together with a conductive material such as conductive tape or epoxy, thereby, protecting the IC substrate against the accumulation of static charges during the assembly of the IC chip on the IC substrate. The IC chip is mounted in the mounting area on the IC substrate and the conductive material is removed before final testing.

摘要翻译： 静电保护集成电路（IC）衬底和制造具有静电保护IC衬底的集成电路封装的方法包括IC衬底，其具有形成在IC衬底的顶部上的多个电迹线，电迹线从 IC芯片安装区域靠近IC基板周围的中心。 将导电电路与导电胶带或环氧树脂等导电材料电气短路，从而在集成电路芯片集成在IC基板上时，保护IC基板免受静电荷的积累。 IC芯片安装在IC基板上的安装区域，导电材料在最终测试之前被去除。

公开(公告)号：US5923047A

公开(公告)日：1999-07-13

申请号：US837618

申请日：1997-04-21

申请人： Chok J. Chia ,  Qwai H. Low ,  Maniam Alagaratnam

发明人： Chok J. Chia ,  Qwai H. Low ,  Maniam Alagaratnam

IPC分类号： G01R31/28 ,  H01L21/301 ,  H01L23/485 ,  H01L23/58 ,  H01L21/60 ,  H01L21/66

CPC分类号： H01L24/06 ,  H01L22/32 ,  G01R31/2884 ,  H01L2224/05553 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/14

摘要： The testing of integrated circuits in a plurality of dice arranged in rows and columns in a semiconductor wafer is facilitated by effectively increasing the pitch between adjacent input/output bonding pads on each die by providing a plurality of test pads in scribing space between adjacent die. Alternate test pads are connected with alternate bonding pads on adjacent die, thereby effectively increasing the pitch of adjacent die for testing. After the integrated circuits are tested and defective circuits are marked, the wafer is scribed in the scribe space and broken to recover the individual die or integrated circuit chips.

摘要翻译： 通过在相邻的管芯之间的刻划空间中提供多个测试焊盘，通过有效地增加每个管芯上相邻的输入/输出焊盘之间的间距，有助于半导体晶片中以行和列布置的多个管芯中的集成电路的测试。 替代的测试焊盘与相邻裸片上的替代焊盘相连，从而有效地增加相邻裸片的间距以进行测试。 在对集成电路进行测试并且标记故障电路之后，在刻划空间刻划晶片并断开晶片以恢复单独的芯片或集成电路芯片。

公开(公告)号：US06861343B2

公开(公告)日：2005-03-01

申请号：US10267410

申请日：2002-10-09

申请人： Chok J. Chia ,  Qwai H. Low ,  Ramaswamy Ranganathan

发明人： Chok J. Chia ,  Qwai H. Low ,  Ramaswamy Ranganathan

IPC分类号： H01L23/367 ,  H01L23/373 ,  H01L23/522 ,  H01L23/552 ,  H01L21/44

CPC分类号： H01L23/552 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit having a top passivation layer and bonding pads, where the improvement is a metal layer overlying all of the integrated circuit. The metal layer overlies the top passivation layer and is not in electrical contact with any of the bonding pads. In this manner, there is a structure that is added to the integrated circuit which has a relatively high thermal conductivity, and which also has a relatively high structural strength. With these two added properties, the occurrence of stress cracks, such as those induced by plastic molded packages, is reduced, and hot spots tend to be dissipated. Thus, the overlying metal layer tends to improve the reliability of the integrated circuit.

摘要翻译： 具有顶部钝化层和接合焊盘的集成电路，其中改进是覆盖所有集成电路的金属层。 金属层覆盖在顶部钝化层上，并且不与任何焊盘焊接。 以这种方式，具有添加到具有相对较高导热性并且还具有相对较高的结构强度的集成电路的结构。 通过这两个添加的性质，减少了由塑料模制包装引起的应力裂纹的发生，并且热点趋于消散。 因此，上覆金属层倾向于提高集成电路的可靠性。

公开(公告)号：US06429534B1

公开(公告)日：2002-08-06

申请号：US09478972

申请日：2000-01-06

申请人： Qwai H. Low ,  Chok J. Chia ,  Maniam Alagaratnam

发明人： Qwai H. Low ,  Chok J. Chia ,  Maniam Alagaratnam

IPC分类号： H01L2348

CPC分类号： H01L23/49827 ,  H01L23/49833 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： Provided is an interposer tape which provides electrical communication between a die and a packaging substrate. The dimensions of the interposer tape may vary to accommodate a variety of die sizes for the same packaging substrate. The interposer tape includes an array of traces. A first set of wire bonds is formed between the array of traces and the die. A second set of wire bonds is formed between the array of traces and the packaging substrate.

摘要翻译： 提供了一种提供管芯和封装衬底之间的电连通的插入器带。 插入器带的尺寸可以变化以适应相同封装基板的各种管芯尺寸。 插入器带包括一列迹线。 在迹线阵列和模具之间形成第一组引线键合。 在迹线阵列和封装衬底之间形成第二组线接合。

公开(公告)号：US06425179B1

公开(公告)日：2002-07-30

申请号：US09417255

申请日：1999-10-12

申请人： Qwai H. Low ,  Chok J. Chia ,  Ramaswamy Ranganathan

发明人： Qwai H. Low ,  Chok J. Chia ,  Ramaswamy Ranganathan

IPC分类号： H01L21/60 ,  H01L23/00 ,  H05K3/34

CPC分类号： H01L24/86 ,  H01L23/562 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00

摘要： According to the present invention, a method for creating a package for a semiconductor die, the package comprising a flexible tape, comprises the following steps. A support with an opening has a plurality of arms extending through at a portion of the opening. For example, for a square opening, there may be eight arms, two extending from each side of the opening. The arms preferably form a “z” shape or some other shape with a transverse component. The flexible tape is then attached to the ends of the arms within the opening such that the flexible tape is supported by the arms. A die is attached to the flexible tape, the die is preferably covered with a molding compound, and the die/flexible tape assembly is scribed from the support, thereby creating an individual package.

摘要翻译： 根据本发明，一种用于制造用于半导体管芯的封装的方法，包括柔性带的封装包括以下步骤。 具有开口的支撑件具有在开口的一部分延伸穿过的多个臂。 例如，对于方形开口，可以有八个臂，两个从开口的每一侧延伸。 臂优选地形成具有横向分量的“z”形或一些其它形状。 然后将柔性带附接到开口内的臂的端部，使得柔性带由臂支撑。 将模具附接到柔性带上，模具优选用模制化合物覆盖，并且模具/柔性带组件从支撑件划刻，从而形成单独的包装。

公开(公告)号：US6114189A

公开(公告)日：2000-09-05

申请号：US927704

申请日：1997-09-10

申请人： Chok J. Chia ,  Seng-Sooi Lim ,  Qwai H. Low

发明人： Chok J. Chia ,  Seng-Sooi Lim ,  Qwai H. Low

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L21/44

CPC分类号： H01L21/565 ,  H01L23/3128 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181

摘要： One aspect of the invention relates to a semiconductor substrate. In one version of the invention, a semiconductor substrate includes a package substrate having first and second surfaces with conductive traces formed thereon and structures for providing electrical connection between selected conductive traces, a die attach area on the first surface of the package substrate adapted to provide physical connection to a semiconductor die, the die attach area having conductive contacts for providing electrical connection between the die and conductive traces on the first surface, a package frame, at least one substrate strap which connects the package substrate to the package frame, the substrate strap being formed integrally with the package substrate and the package frame.

摘要翻译： 本发明的一个方面涉及一种半导体衬底。 在本发明的一个实施例中，半导体衬底包括具有形成在其上的导电迹线的第一和第二表面的封装衬底，以及用于在所选择的导电迹线之间提供电连接的结构，适于提供包装衬底的第一表面上的管芯附着区域 与半导体管芯的物理连接，管芯附接区域具有用于在管芯和第一表面上的导电迹线之间提供电连接的导电触点，封装框架，将封装衬底连接到封装框架的至少一个衬底带，衬底 带子与封装基板和封装框架整体形成。

公开(公告)号：US6057594A

公开(公告)日：2000-05-02

申请号：US842379

申请日：1997-04-23

申请人： Chok J. Chia ,  Qwai H. Low ,  Maniam Alagaratnam

发明人： Chok J. Chia ,  Qwai H. Low ,  Maniam Alagaratnam

IPC分类号： H01L23/433 ,  H01L23/495 ,  H01L23/498 ,  H01L23/34 ,  H01L23/48

CPC分类号： H01L23/4334 ,  H01L23/49572 ,  H01L23/49816 ,  H01L2924/0002

摘要： A molded tape ball grid array package has a base structure including a heat conductive substrate and flex tape extending from opposing regions on a surface of the substrate with molded plastic material between the flex tape and the substrate. The flex tape has at least one conductive metal lead pattern which can be positioned on a side of the tape facing the substrate with a plurality of apertures exposing the conductive lead pattern from an opposing side of the tape for solder ball bonding. A semiconductor integrated circuit chip is mounted to a central portion of the substrate between the opposing regions of the flex tape with wire bonding interconnecting bond pads on the chip to the metal lead pattern. The chip and wire bonding are then encapsulated on the substrate. The structure is economical and permits high power dissipation from an integrated circuit. The molding process in fabricating the integrated circuit package is economical and readily implemented using injection molding.

摘要翻译： 模制的带状球栅阵列封装具有基底结构，其包括导热基底和柔性带，该柔性带从柔性带和基底之间的模制塑料材料的表面上的相对区域延伸。 柔性带具有至少一个导电金属引线图案，其可以被定位在面向基板的带的一侧，并具有多个孔，用于将导电引线图案从带的相对侧暴露以进行焊球接合。 半导体集成电路芯片通过引线将芯片上的接合焊盘互连到金属引线图案，在柔性带的相对区域之间的基板的中心部分上安装。 然后将芯片和引线接合封装在基板上。 该结构是经济的并且允许来自集成电路的高功率耗散。 在制造集成电路封装中的成型工艺是经济的，并且易于使用注塑成型。