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    MEMORY WITH REFRESH LOGIC TO ACCOMODATE LOW-RETENTION STORAGE ROWS
    12.
    发明申请
    MEMORY WITH REFRESH LOGIC TO ACCOMODATE LOW-RETENTION STORAGE ROWS 有权
    具有刷新逻辑的存储器来保存低保持存储条

    公开(公告)号：US20140293725A1

    公开(公告)日：2014-10-02

    申请号：US14306174

    申请日：2014-06-16

    Applicant: Rambus Inc.

    Inventor： Scott C. Best ,  Ely Tsern

    IPC: G11C11/406

    CPC classification number: G11C11/406 ,  G06F13/1636 ,  G11C2211/4061

    Abstract: An apparatus is disclosed that includes a memory controller chip and memory chips packaged with the memory controller chip. Each memory chip includes normal-retention storage rows that exhibit retention times greater or equal to a first time interval, and having been tested to generate information identifying low-retention storage rows that exhibit retention times less than the first time interval. Refresh logic refreshes the normal-retention storage rows at a first refresh rate corresponding to the first time interval, and refreshes each low-retention storage row at a second refresh rate that is greater than the first refresh rate.

    Abstract translation: 公开了一种包括与存储器控制器芯片封装的存储器控​​制器芯片和存储器芯片的装置。 每个存储器芯片包括呈现大于或等于第一时间间隔的保持时间的正常保留存储行，并且已经被测试以生成标识低保留存储行的信息，其表现出小于第一时间间隔的保留时间。 刷新逻辑以对应于第一时间间隔的第一刷新速率刷新正常保留存储行，并且以大于第一刷新率的第二刷新率刷新每个低保留存储行。

    MEMORY REPAIR METHOD AND APPARATUS BASED ON ERROR CODE TRACKING
    18.
    发明申请
    MEMORY REPAIR METHOD AND APPARATUS BASED ON ERROR CODE TRACKING 有权

    公开(公告)号：US20230028438A1

    公开(公告)日：2023-01-26

    申请号：US17852272

    申请日：2022-06-28

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern

    IPC: G06F11/10 ,  G06F11/16 ,  G11C29/42 ,  G11C29/44 ,  G11C7/10 ,  G11C29/52 ,  G11C29/00 ,  H03M13/15

    Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

    Memory System Topologies Including A Memory Die Stack
    19.
    发明申请
    Memory System Topologies Including A Memory Die Stack 有权

    公开(公告)号：US20210375351A1

    公开(公告)日：2021-12-02

    申请号：US17323889

    申请日：2021-05-18

    Applicant: Rambus Inc.

    Inventor： Ian Shaeffer ,  Ely Tsern ,  Craig Hampel

    IPC: G11C11/4093 ,  H01L25/065 ,  H01L25/10 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G06F13/40 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

    Memory system topologies including a memory die stack
    20.
    发明授权
    Memory system topologies including a memory die stack 有权

    公开(公告)号：US11043258B2

    公开(公告)日：2021-06-22

    申请号：US16842368

    申请日：2020-04-07

    Applicant: Rambus Inc.

    Inventor： Ian Shaeffer ,  Ely Tsern ,  Craig Hampel

    IPC: G11C7/00 ,  G11C11/4093 ,  H01L25/065 ,  H01L25/10 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G06F13/40 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  H01L25/18 ,  H01L23/00

    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

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