公开(公告)号：US20170222039A1

公开(公告)日：2017-08-03

申请号：US15421920

申请日：2017-02-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi YANAGIGAWA ,  Hiroyoshi KUDOU

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L21/26513 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7802

Abstract: A semiconductor device according to one embodiment includes a semiconductor substrate having a main surface and a back surface opposite to the main surface, a drift region of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity type, and a gate electrode. The semiconductor substrate has a trench in the main surface. The gate electrode is formed in the trench. A distribution of an impurity concentration in the base region has a plurality of peak values along a direction of depth from the main surface toward the back surface, and the number of peak values is four or more.

公开(公告)号：US20160308529A1

公开(公告)日：2016-10-20

申请号：US15091827

申请日：2016-04-06

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi YANAGIGAWA

IPC: H03K17/687 ,  H01L27/088 ,  H01L29/36

CPC classification number: H03K17/6871 ,  H01L21/823487 ,  H01L27/0266 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/36 ,  H01L29/7813 ,  H03K17/06 ,  H03K17/6874

Abstract: A semiconductor device and a circuit arrangement are provided so as to reduce an on resistance. A first power MOS transistor and a second power MOS transistor are formed on the same semiconductor substrate. A first power MOS transistor formed in a first element formation region has a columnless structure including no columns. The second power MOS transistor formed in a second element formation region has an SJ structure including columns.

Abstract translation: 提供半导体器件和电路布置以便降低导通电阻。 第一功率MOS晶体管和第二功率MOS晶体管形成在同一半导体衬底上。 形成在第一元件形成区域中的第一功率MOS晶体管具有不包括列的无柱结构。 形成在第二元件形成区域中的第二功率MOS晶体管具有包括列的SJ结构。

公开(公告)号：US20240243198A1

公开(公告)日：2024-07-18

申请号：US18407125

申请日：2024-01-08

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi YANAGIGAWA ,  Yasutaka NAKASHIBA ,  Kazuhisa MORI ,  Koichi HASEGAWA

IPC: H01L29/78 ,  G01K7/01 ,  H01L23/00 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7813 ,  G01K7/01 ,  H01L24/45 ,  H01L24/48 ,  H01L29/0696 ,  H01L29/66734 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48464 ,  H01L2224/48472 ,  H01L2924/13091

Abstract: According to this present application, a reliability of a semiconductor device can be improved. The semiconductor device has a first region where a MOSFET is formed, and a second region where a temperature sensor transistor is formed. A body region is formed in a semiconductor substrate of the first region, and a base region is formed in the semiconductor substrate of the second region. A source region is formed in the body region and an emitter region is formed in the base region. A first column region is formed in the semiconductor substrate located below the body region, and a second column region is formed in the semiconductor substrate located below the base region.

公开(公告)号：US20230246002A1

公开(公告)日：2023-08-03

申请号：US18059646

申请日：2022-11-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA ,  Hiroshi YANAGIGAWA ,  Kazuhisa MORI ,  Toshiyuki HATA

IPC: H01L25/07 ,  H01L23/00 ,  H01L29/78

CPC classification number: H01L25/074 ,  H01L24/32 ,  H01L24/40 ,  H01L24/73 ,  H01L29/7805 ,  H01L29/7813 ,  H01L2224/32145 ,  H01L2224/40227 ,  H01L2224/73263 ,  H01L2924/13091 ,  H02M7/537

Abstract: A semiconductor device includes: a first semiconductor chip including a first MOSFET of n-type and a first parasitic diode; and a second semiconductor chip including a second MOSFET of n-type and a second parasitic diode. A first source electrode and a first gate wiring are formed in a first front surface of the first semiconductor chip, and a first drain electrode is formed in a first back surface of the first semiconductor chip. A second source electrode and a second gate wiring are formed in a second front surface of the second semiconductor chip, and a second drain electrode is formed in a second back surface of the second semiconductor chip. The first front surface and the second front surface face each other such that the first source electrode and the second source electrode are in contact with each other via a conductive paste.

公开(公告)号：US20210217844A1

公开(公告)日：2021-07-15

申请号：US17115204

申请日：2020-12-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi YANAGIGAWA ,  Katsumi EIKYU ,  Masami SAWADA ,  Akihiro SHIMOMURA ,  Kazuhisa MORI

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: In a trench gate type power MOSFET having a super-junction structure, both improvement of a breakdown voltage of a device and reduction of on-resistance are achieved. The trench gate and a column region are arranged so as to be substantially orthogonal to each other in a plan view, and a base region (channel forming region) and the column region are arranged separately in a cross-sectional view.

公开(公告)号：US20190097008A1

公开(公告)日：2019-03-28

申请号：US16121346

申请日：2018-09-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi YANAGIGAWA

IPC: H01L29/423 ,  H01L29/08 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/78

Abstract: A semiconductor device which simplifies the manufacturing process while decreasing the width of separation between a first MOS transistor area and a second MOS transistor area, and a method for manufacturing the semiconductor device. A first MOS transistor and a second MOS transistor configure a bidirectional switch. The first MOS transistor and second MOS transistor each have a vertical trench structure. A first impurity region abuts on the side wall of a first gate trench of a first MOS transistor element outside the first MOS transistor area and is electrically coupled to a first source region.

公开(公告)号：US20160043714A1

公开(公告)日：2016-02-11

申请号：US14806022

申请日：2015-07-22

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi YANAGIGAWA

IPC: H03K17/687

CPC classification number: H03K17/687 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/181 ,  H03K17/08104 ,  H03K2217/0063 ,  H03K2217/0072 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: The present invention is provided to easily manufacture an IPD as any of a high-side switch and a low-side switch. A level shifting circuit is coupled to an input terminal, a first terminal, and a grounding terminal. Drive power of the level shifting circuit is supplied from the first terminal. An output signal of the level shifting circuit is input to a driver circuit. The driver circuit is coupled to the first terminal and a second terminal. Drive power of the driver circuit is supplied from the first terminal. A transistor has a gate electrode coupled to the driver circuit, a source coupled to the second terminal, and a drain coupled to a third terminal.

Abstract translation: 提供本发明以容易地制造作为高侧开关和低侧开关中的任何一个的IPD。 电平移位电路耦合到输入端子，第一端子和接地端子。 电平移位电路的驱动电源由第一端子提供。 电平移位电路的输出信号被输入到驱动电路。 驱动器电路耦合到第一端子和第二端子。 从第一终端提供驱动电路的驱动电力。 晶体管具有耦合到驱动器电路的栅电极，耦合到第二端子的源极和耦合到第三端子的漏极。