公开(公告)号：US07099539B1

公开(公告)日：2006-08-29

申请号：US10615318

申请日：2003-07-07

申请人： Chi Au ,  Tzu-Yih Chu ,  Hao Yin ,  Abraham C. Ma ,  Edward W. Lee

发明人： Chi Au ,  Tzu-Yih Chu ,  Hao Yin ,  Abraham C. Ma ,  Edward W. Lee

IPC分类号： G02B6/26

CPC分类号： G02B6/2746 ,  G02B6/125 ,  G02B6/266

摘要： An optical system and associated method are provided. Included is a first branch capable of allowing light to pass therethrough in a forward direction and a reverse direction. The first branch includes a first medium with a first refractive index (n1), and a first end and a second end. Also included is a second branch capable of allowing light to pass therethrough in the forward direction. The second branch includes a second medium with a second refractive index (n2, with n2

摘要翻译： 提供了一种光学系统及相关方法。 包括能够使光从正向和反方向通过的第一分支。 第一分支包括具有第一折射率（n <1> 1）的第一介质，以及第一端和第二端。 还包括能够允许光沿正向通过的第二分支。 第二分支包括第二介质，其具有第二折射率（n _{2，n≥2 <= SIN＆lt; 1＆gt;（n2 / n＆lt; 1＆gt; 通过第一分支的光通过第二分支，其中θ1是从第一分支到第二分支的反向通过的光的入射角。}

公开(公告)号：US06522462B2

公开(公告)日：2003-02-18

申请号：US09682283

申请日：2001-08-14

申请人： Tzu-Yih Chu ,  Shyang Chang ,  Chi Au ,  Abraham C. Ma

发明人： Tzu-Yih Chu ,  Shyang Chang ,  Chi Au ,  Abraham C. Ma

IPC分类号： H01S300

CPC分类号： G02F2/004 ,  G02B6/26 ,  G02B6/29352 ,  G02F3/00 ,  G02F2203/70

摘要： Optical logic gates are constructed from Mach-Zehnder Interferometer (MZI) optical circuits. A multi-mode interference (MMI) splitter divides a continuous-wave input into two branches of the interferometer. Each branch has a semiconductor optical amplifier (SOA). When a logic input having a logic-high power level is applied to one of the SOA's, cross-phase modulation occurs in the SOA. The phase shift increases through the SOA. The branch coupled to the logic input has a relative phase shift of &pgr; compared with the other branch. When two branches with the &pgr; phase difference are combined, destructive interference occurs, producing a logic low. An MMI combiner or an equivalent phase shifter is used to combine the two branches. The MMI splitter adds a phase shift of &pgr;/2 to the upper branch but not to the lower branch, while the MMI combiner also adds &pgr;/2 shifts.

摘要翻译： 光逻辑门由Mach-Zehnder干涉仪（MZI）光电路构成。 多模干扰（MMI）分离器将连续波输入分成干涉仪的两个分支。 每个分支都有一个半导体光放大器（SOA）。 当具有逻辑高功率电平的逻辑输入被应用于SOA中的一个时，在SOA中发生交叉相位调制。 相移通过SOA增加。 耦合到逻辑输入的分支与其他分支相比具有pi的相对相移。 当具有pi相位差的两个分支组合时，发生相消干扰，产生逻辑低电平。 使用MMI组合器或等效移相器来组合两个分支。 MMI分路器将pi / 2的相移添加到上分支，但不分配给下分支，而MMI组合器也增加pi / 2移位。

公开(公告)号：US07930531B2

公开(公告)日：2011-04-19

申请号：US11838192

申请日：2007-08-13

申请人： David Q. Chow ,  Charles C. Lee ,  Frank Yu ,  Tzu-Yih Chu ,  Ming-Shiang Shen

发明人： David Q. Chow ,  Charles C. Lee ,  Frank Yu ,  Tzu-Yih Chu ,  Ming-Shiang Shen

IPC分类号： G06F1/00

CPC分类号： G06F21/568 ,  G06F21/575 ,  G06F2221/2105 ,  G06F2221/2153

摘要： A multi-partition Universal Serial Bus (USB) device has a flash memory with multiple partitions of storage. Some partitions are for different operating systems and store OS images. Another partition has a control program while a user partition stores user data and user configuration information. The control program can test the multi-partition USB device and instruct the host computer BIOS to mount a partition from its flash memory as a drive of the host computer. The host computer can then be rebooted. The OS image from the flash memory is loaded into main memory during rebooting, and the host computer executes a new operating system using the new OS image. The user can press buttons on the multi-partition USB device to select which OS to load, and to begin rebooting. Virus removal programs in the alternate OS can help recover from a virus in the primary OS.

摘要翻译： 多分区通用串行总线（USB）设备具有具有多个存储分区的闪存。 一些分区用于不同的操作系统并存储操作系统映像。 另一个分区具有控制程序，而用户分区则存储用户数据和用户配置信息。 控制程序可以测试多分区USB设备，并指示主机BIOS将其闪存中的分区作为主机的驱动器安装。 然后可以重新启动主机。 重新启动时，闪存中的OS映像将加载到主内存中，主机使用新的操作系统映像执行新的操作系统。 用户可以按多分区USB设备上的按钮选择要加载的操作系统，并开始重新启动。 备用操作系统中的病毒清除程序可以帮助从主操作系统中的病毒恢复。

公开(公告)号：US20050160218A1

公开(公告)日：2005-07-21

申请号：US10761853

申请日：2004-01-20

申请人： Sun-Teck See ,  Tzu-Yih Chu ,  Ben-Wei Chen ,  Horng-yee Chou ,  Szu-Kuang Chou ,  Charles Lee

发明人： Sun-Teck See ,  Tzu-Yih Chu ,  Ben-Wei Chen ,  Horng-yee Chou ,  Szu-Kuang Chou ,  Charles Lee

IPC分类号： G06F3/06 ,  G06F12/00 ,  G06F13/16 ,  G06F13/40

CPC分类号： G06F13/405 ,  G06F3/0601 ,  G06F13/1694 ,  G06F2003/0694

摘要： A FLASH controller is disclosed. The controller comprises a USB interface unit. The USB interface unit implements a USB standard that has a bus speed equal or greater than 12 Mb/s. The controller includes an internal bus coupled to the USB interface unit; and a FLASH interface unit coupled to the internal bus. The FLASH interface unit includes FLASH controller logic that allows the throughput for access to the FLASH memory to match the speed of the USB standard. Advantages of the FLASH controller in accordance with the present invention include (1) utilizing the higher speed USB interface such as the USB 2.0 standard, which substantially increases the serial throughput between USB host and FLASH controller; (2) utilizing more advanced FLASH control logic which is implemented to raise the throughput for the FLASH memory access; (3) utilizing an intelligent algorithm to detect and access the different FLASH types, which broadens the sourcing and the supply of FLASH memory; (4) by storing the software program along with data in FLASH memory which results in the cost of the controller being reduced, and also makes the software program field changeable and upgradeable; and (5) providing high integration, which substantially reduces the overall space needed and reduces the complexity and the cost of manufacturing.

摘要翻译： 公开了一种闪存控制器。 控制器包括USB接口单元。 USB接口单元实现总线速度等于或大于12 Mb / s的USB标准。 该控制器包括耦合到USB接口单元的内部总线; 以及耦合到内部总线的FLASH接口单元。 FLASH接口单元包括FLASH控制器逻辑，允许访问闪速存储器的吞吐量与USB标准的速度相匹配。 根据本发明的闪存控制器的优点包括（1）利用诸如USB 2.0标准的更高速USB接口，其大大增加了USB主机和闪存控制器之间的串行吞吐量; （2）利用更高级的FLASH控制逻辑，其实现以提高FLASH存储器访问的吞吐量; （3）利用智能算法检测和访问不同的FLASH类型，拓宽了FLASH存储器的采购和供应; （4）通过将软件程序与FLASH存储器中的数据一起存储，从而降低控制器的成本，并使软件程序区域可以更改和升级; 和（5）提供高集成度，这大大降低了所需的总体空间并降低了制造的复杂性和成本。

公开(公告)号：US5941447A

公开(公告)日：1999-08-24

申请号：US162430

申请日：1998-09-28

申请人： Tzu-Yih Chu ,  Abraham C. Ma

发明人： Tzu-Yih Chu ,  Abraham C. Ma

IPC分类号： G11C5/00 ,  G11C8/12 ,  H05K1/02 ,  H05K1/16 ,  B23K31/02

CPC分类号： G11C5/06 ,  G11C5/04 ,  G11C5/14 ,  G11C8/12 ,  H05K1/0231 ,  H05K1/023 ,  H05K1/162 ,  H05K2201/0187 ,  H05K2201/10022 ,  H05K2201/10515 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10689

摘要： A processor module has a cache of SRAM chips mounted on both a back and a front surface but de-coupling capacitors mounted on only the back surface. Each de-coupling capacitor is for suppressing current spikes from a pair of SRAM chips. The pair of SRAM chips includes a first SRAM chip on the same surface as the capacitor and a second SRAM chip opposite the first SRAM chip on the front surface of the module. The first SRAM chip belongs to a first bank while the second SRAM chip belongs to a second bank. Two chip-enable signals control access to the two banks. Since only one bank is accessed at any time, and access causes current spikes, only one bank and only one SRAM chip in the pair of SRAM chips creates a current spike at any time. Thus, a capacitor can be shared between the two SRAM chips in the pair. The shared capacitor can be mounted next to or under one of the SRAM chips, or formed within the multi-layer substrate itself. Having capacitors on only one of the surfaces reduces the number of placement sequences required, reducing manufacturing cost. The capacitors are mounted on the opposite surface from the large processor for efficiency.

摘要翻译： 处理器模块具有安装在背面和前表面上的SRAM芯片的高速缓存，但是只耦合安装在背面上的电容器。 每个去耦电容器用于抑制来自一对SRAM芯片的电流尖峰。 这对SRAM芯片包括与电容器相同表面上的第一SRAM芯片和与模块前表面上的第一SRAM芯片相对的第二SRAM芯片。 第一个SRAM芯片属于第一个bank，而第二个SRAM芯片属于第二个bank。 两个芯片使能信号控制对两个存储体的访问。 由于在任何时间只访问一个存储区，访问引起电流尖峰，所以SRAM对中的只有一个存储体和只有一个SRAM芯片可以随时创建电流尖峰。 因此，可以在该对中的两个SRAM芯片之间共享电容器。 共享电容器可以安装在SRAM芯片旁边或下面，或者形成在多层基板本身内。 仅在其中一个表面上放置电容器可减少所需的放置顺序数量，从而降低制造成本。 电容器安装在与大型处理器相反的表面上，以提高效率。

公开(公告)号：US20050146491A1

公开(公告)日：2005-07-07

申请号：US10707622

申请日：2003-12-24

申请人： Ching-Jong Su ,  Sun-Teck See ,  Tzu-Yih Chu

发明人： Ching-Jong Su ,  Sun-Teck See ,  Tzu-Yih Chu

IPC分类号： G09G3/36

CPC分类号： G11C16/06 ,  Y10S345/905

摘要： A multi-light-emitting diode (LED) display for a USB flash drive produces a visually dazzling display. When accessed, a USB flash controller drives pulses onto an activity signal that increments a counter on a pattern-decoding generator. The pattern-decoding generator decodes the count and drives signals to data outputs. The data outputs connect to LED's, turning LED's on and off according to a display pattern. The pattern can be programmed by the USB flash controller into the pattern-decoding generator, or can be a hardwired pattern. Marquee patterns having a lit LED appearing to move down a line of LED's have more visual appeal than single LED indicators. Each data line can drive two LED's in different parts of a dual display, reducing costs. Multi-color LED's can be used to improve variety. The multiple LED's and the pattern-decoding generator can be mounted on a flexible PCB.

摘要翻译： 用于USB闪存驱动器的多发光二极管（LED）显示器产生视觉上令人眼花缭乱的显示。 当访问时，USB闪存控制器将脉冲驱动到增加模式解码发生器上的计数器的活动信号上。 模式解码产生器解码计数并将信号驱动到数据输出。 数据输出连接到LED，根据显示模式打开和关闭LED。 该模式可以由USB闪存控制器编程到模式解码生成器中，也可以是硬连线图案。 具有点亮LED的花纹图案看起来沿着LED线移动，具有比单个LED指示器更多的视觉吸引力。 每个数据线可以驱动双显示器的不同部分的两个LED，从而降低成本。 多色LED可用于提高品种。 多个LED和图案解码发生器可以安装在柔性PCB上。

公开(公告)号：US20050114587A1

公开(公告)日：2005-05-26

申请号：US10707138

申请日：2003-11-22

申请人： Horng-Yee Chou ,  Sun-Teck See ,  Tzu-Yih Chu

发明人： Horng-Yee Chou ,  Sun-Teck See ,  Tzu-Yih Chu

IPC分类号： G06F12/00 ,  G06F13/38

CPC分类号： G06F13/385

摘要： An ExpressCard contains flash memory. The ExpressCard has an ExpressCard connector that plugs into a host, such as a personal computer, digital camera, or personal digital assistant (PDA). A controller chip on the ExpressCard uses a pair of differential Universal-Serial-Bus (USB) data lines in the connector to communicate with the USB host, or can use PCI Express, Firewire, or other protocols. One or more flash-memory chips on the ExpressCard are controlled by a flash-memory controller in the controller chip. Two or more channels of a flash bus have a shared control bus but separate ready lines. The separate ready lines allow flash-memory chips in the two channels to finish operations at different times.

摘要翻译： ExpressCard包含闪存。 ExpressCard具有插入主机的ExpressCard连接器，如个人计算机，数码相机或个人数字助理（PDA）。 ExpressCard上的控制器芯片使用连接器中的一对差分通用串行总线（USB）数据线与USB主机进行通信，也可以使用PCI Express，Firewire或其他协议。 ExpressCard上的一个或多个闪存芯片由控制器芯片中的闪存控制器控制。 闪存总线的两个或更多个通道具有共享控制总线，但是分离的就绪线路。 单独的就绪线路允许两个通道中的闪存芯片在不同时间完成操作。

公开(公告)号：US05996880A

公开(公告)日：1999-12-07

申请号：US56152

申请日：1998-04-06

申请人： Tzu-Yih Chu ,  Abraham C. Ma

发明人： Tzu-Yih Chu ,  Abraham C. Ma

IPC分类号： G11C5/00 ,  G11C8/12 ,  H05K1/02 ,  H05K1/16 ,  B23K31/02

CPC分类号： G11C5/06 ,  G11C5/04 ,  G11C5/14 ,  G11C8/12 ,  H05K1/0231 ,  H05K1/023 ,  H05K1/162 ,  H05K2201/0187 ,  H05K2201/10022 ,  H05K2201/10515 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10689

摘要： A memory module has DRAM chips mounted on both a front and a back surface but decoupling capacitors mounted on only the front surface. Each decoupling capacitor is for suppressing current spikes from a pair of DRAM chips. The pair of DRAM chips includes a first DRAM chip on the same surface as the capacitor and a second DRAM chip opposite the first DRAM chip on the back surface of the module. The first DRAM chip belongs to a first bank while the second DRAM chip belongs to a second bank. Two RAS signals are for controlling access to the two banks. Since only one bank is accessed at any time, and access causes current spikes, only one bank and only one DRAM chip in the pair of DRAM chips creates a current spike at any time. Thus a capacitor can be shared between the two DRAM chips in the pair. The shared capacitor can be mounted next to or under one of the DRAM chips, or formed within the multi-layer substrate itself. Having capacitors on only one of the surfaces reduces the number of placement sequences required, reducing manufacturing cost.

摘要翻译： 存储器模块具有安装在前表面和后表面上的DRAM芯片，但是仅去除仅安装在前表面上的电容器。 每个去耦电容器用于抑制来自一对DRAM芯片的电流尖峰。 一对DRAM芯片包括与电容器相同的表面上的第一DRAM芯片和与模块背面上的第一DRAM芯片相对的第二DRAM芯片。 第一DRAM芯片属于第一存储体，而第二DRAM芯片属于第二存储体。 两个RAS信号用于控制对两个银行的访问。 由于在任何时间只访问一个存储体，访问引起电流尖峰，所以DRAM芯片对中只有一个存储体和只有一个DRAM芯片可以随时创建电流尖峰。 因此，可以在该对中的两个DRAM芯片之间共享电容器。 共享电容器可以安装在DRAM芯片旁边或下面，或者形成在多层基板本身内。 仅在其中一个表面上放置电容器可减少所需的放置顺序数量，从而降低制造成本。

公开(公告)号：US5856937A

公开(公告)日：1999-01-05

申请号：US876135

申请日：1997-06-23

申请人： Tzu-Yih Chu ,  Abraham C. Ma

发明人： Tzu-Yih Chu ,  Abraham C. Ma

IPC分类号： G11C5/00 ,  G11C8/12 ,  H05K1/02 ,  H05K1/16 ,  G11C5/02

CPC分类号： G11C5/06 ,  G11C5/04 ,  G11C5/14 ,  G11C8/12 ,  H05K1/0231 ,  H05K1/023 ,  H05K1/162 ,  H05K2201/0187 ,  H05K2201/10022 ,  H05K2201/10515 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10689

摘要： A processor module has a cache of SRAM chips mounted on both a back and a front surface but de-coupling capacitors mounted on only the back surface. Each de-coupling capacitor is for suppressing current spikes from a pair of SRAM chips. The pair of SRAM chips includes a first SRAM chip on the same surface as the capacitor and a second SRAM chip opposite the first SRAM chip on the front surface of the module. The first SRAM chip belongs to a first bank while the second SRAM chip belongs to a second bank. Two chip-enable signals control access to the two banks. Since only one bank is accessed at any time, and access causes current spikes, only one bank and only one SRAM chip in the pair of SRAM chips creates a current spike at any time. Thus, a capacitor can be shared between the two SRAM chips in the pair. The shared capacitor can be mounted next to or under one of the SRAM chips, or formed within the multi-layer substrate itself. Having capacitors on only one of the surfaces reduces the number of placement sequences required, reducing manufacturing cost. The capacitors are mounted on the opposite surface from the large processor for efficiency.

摘要翻译： 处理器模块具有安装在背面和前表面上的SRAM芯片的高速缓存，但是只耦合安装在背面上的电容器。 每个去耦电容器用于抑制来自一对SRAM芯片的电流尖峰。 这对SRAM芯片包括与电容器相同表面上的第一SRAM芯片和与模块前表面上的第一SRAM芯片相对的第二SRAM芯片。 第一个SRAM芯片属于第一个bank，而第二个SRAM芯片属于第二个bank。 两个芯片使能信号控制对两个存储体的访问。 由于在任何时间只访问一个存储区，访问引起电流尖峰，所以SRAM对中的只有一个存储体和只有一个SRAM芯片可以随时创建电流尖峰。 因此，可以在该对中的两个SRAM芯片之间共享电容器。 共享电容器可以安装在SRAM芯片旁边或下面，或者形成在多层基板本身内。 仅在其中一个表面上放置电容器可减少所需的放置顺序数量，从而降低制造成本。 电容器安装在与大型处理器相反的表面上，以提高效率。

公开(公告)号：US20090013165A1

公开(公告)日：2009-01-08

申请号：US11846476

申请日：2007-08-28

申请人： David Q. Chow ,  Tzu-Yih Chu ,  Frank I. Yu ,  Ben W. Chen ,  Ming-Shiang Shen

发明人： David Q. Chow ,  Tzu-Yih Chu ,  Frank I. Yu ,  Ben W. Chen ,  Ming-Shiang Shen

IPC分类号： G06F15/177

CPC分类号： G06F9/4406 ,  G06F9/44505 ,  G06F21/568 ,  G06F21/575 ,  G06F2221/2105 ,  G06F2221/2153

摘要： Techniques for booting a host computer from a portable storage device with customized settings have been described herein. According to one embodiment, in response to detecting a portable storage device inserted into a first host computer having a first operating environment provided by a first operating system (OS) installed in the first host computer, rebooting the first host computer into a second operating environment using a second OS image stored in the portable device. In addition, a personal configuration file stored in the portable device is extracted to configure the second operating environment of the first host computer, such that the user of the portable storage device can operate the second host computer in view of the personal working environment. Other methods and apparatuses are also described.

摘要翻译： 这里已经描述了用于通过定制设置从便携式存储设备引导主计算机的技术。 根据一个实施例，响应于检测到插入具有由安装在第一主机计算机中的第一操作系统（OS）提供的第一操作环境的第一主机计算机的便携式存储设备，将第一主计算机重新启动到第二操作环境 使用存储在便携式设备中的第二OS图像。 此外，提取存储在便携式设备中的个人配置文件以配置第一主计算机的第二操作环境，使得便携式存储设备的用户可以根据个人工作环境来操作第二主计算机。 还描述了其它方法和装置。