公开(公告)号：US20160197066A1

公开(公告)日：2016-07-07

申请号：US14928780

申请日：2015-10-30

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Uchida ,  Takafumi Kuramoto ,  Risho Koh

IPC: H01L25/00 ,  H01L49/02 ,  H01L23/522 ,  H01L21/56 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02 ,  H01L25/065 ,  H01L21/768

CPC classification number: H01L21/56 ,  H01L21/02164 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/3192 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/562 ,  H01L23/564 ,  H01L23/58 ,  H01L28/10 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2924/0002 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An improvement is achieved in the reliability of a semiconductor device by preventing a dielectric breakdown between two semiconductor chips facing each other. During the manufacturing of first and second semiconductor chips, the process of planarizing the upper surfaces of insulating films is performed. Then, the first and second semiconductor chips are stacked via an insulating sheet with the respective insulating films of the first and second semiconductor chips facing each other such that the respective coils of the first and second semiconductor chips are magnetically coupled to each other.

Abstract translation: 通过防止两个彼此面对的半导体芯片之间的电介质击穿，可以提高半导体器件的可靠性。 在制造第一和第二半导体芯片期间，执行绝缘膜的上表面的平坦化处理。 然后，第一半导体芯片和第二半导体芯片通过绝缘片堆叠，其中第一和第二半导体芯片的各个绝缘膜彼此面对，使得第一和第二半导体芯片的各个线圈彼此磁耦合。

公开(公告)号：US11276640B2

公开(公告)日：2022-03-15

申请号：US16577228

申请日：2019-09-20

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Uchida

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/58

Abstract: A semiconductor device includes a plurality of first wires formed in a first layer, a plurality of second wires formed to intersect the plurality of first wires in a second layer stacked on the first layer, a plurality of first vias formed at intersections of the plurality of first wires and the plurality of second wires, and an inductor formed in a third layer stacked on the first layer and the second layer.

公开(公告)号：US09632119B2

公开(公告)日：2017-04-25

申请号：US14475623

申请日：2014-09-03

Applicant: Renesas Electronics Corporation

Inventor： Takatsugu Nemoto ,  Yasutaka Nakashiba ,  Takasuke Hashimoto ,  Shinichi Uchida ,  Kazunori Go ,  Hiroshi Oe ,  Noriko Yoshikawa

IPC: G01R21/00 ,  H01F21/00 ,  G01R15/18

CPC classification number: H01L23/5227 ,  G01R15/181 ,  G01R21/00 ,  G01R31/2607 ,  G01R33/06 ,  H01F21/00 ,  H01F27/2804 ,  H01L23/5286 ,  H01L28/10

Abstract: A sensor device includes a printed circuit board, a power line, a first semiconductor device, and a second semiconductor device. The first semiconductor device includes a first inductor, and the second semiconductor device includes a second inductor. Each inductor is formed using an interconnect layer. The power line extends between the two inductors without overlapping the first and second inductor, when viewed from a direction perpendicular to a main surface of the printed circuit board.

公开(公告)号：US09263403B2

公开(公告)日：2016-02-16

申请号：US14706387

申请日：2015-05-07

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Uchida

IPC: H01L27/08 ,  H01L21/8238 ,  H01L23/64 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5283 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/585 ,  H01L2223/6611 ,  H01L2924/0002 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate, a first wiring layer including a plurality of first dummy metals provided inside an inductor wiring, a plurality of second dummy metals provided outside the inductor wiring, and a plurality of third dummy metals provided to overlap the inductor wiring in a plan view, and a second wiring layer provided between the semiconductor substrate and the first wiring layer. The second wiring layer includes the inductor wiring formed in the second wiring layer, a first region surrounding the inductor wiring which includes a plurality of fourth dummy metals, and a second region surrounding the first region which includes a plurality of fifth dummy metals. A density of the fourth dummy metals is lower than a density of the fifth dummy metals.

Abstract translation: 半导体器件包括半导体衬底，设置在电感器布线内部的多个第一虚拟金属的第一布线层，设置在电感器布线外部的多个第二虚设金属和设置成与电感器布线重叠的多个第三虚设金属 以及设置在半导体衬底和第一布线层之间的第二布线层。 第二布线层包括形成在第二布线层中的电感器布线，围绕包括多个第四虚设金属的电感器布线的第一区域和围绕包括多个第五虚拟金属的第一区域的第二区域。 第四虚拟金属的密度低于第五虚拟金属的密度。

公开(公告)号：US09029982B2

公开(公告)日：2015-05-12

申请号：US14228987

申请日：2014-03-28

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Uchida

IPC: H01L27/08 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/58 ,  H01L23/64 ,  H01L23/66 ,  H01L29/86

CPC classification number: H01L23/5283 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/585 ,  H01L2223/6611 ,  H01L2924/0002 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate, and a multilayer wiring layer provided over the semiconductor substrate. The multilayer wiring layer includes an inductor wiring formed in one wiring layer, a plurality of first dummy metals formed in the same layer as the inductor and provided inside the inductor, a plurality of second dummy metals formed in a same layer as the inductor and provided outside the inductor, a plurality of third dummy metals formed in a layer lower than the one wiring layer including the inductor, and provided inside the inductor in a plan view, a plurality of fourth dummy metals formed in a same layer as the plurality of third dummy metals and provided outside the inductor in the plan view, and a plurality of fifth dummy metals formed in the same layer as the plurality of third dummy metals and provided to overlap with the inductor.

Abstract translation: 半导体器件包括半导体衬底和设置在半导体衬底上的多层布线层。 所述多层布线层包括形成在一个布线层中的电感器布线，与所述电感器形成在与所述电感器相同的层中并设置在所述电感器内的多个第一伪金属，形成在与所述电感器相同的层中的多个第二伪金属， 在电感器的外部，形成在比包括电感器的一个布线层低的层中的多个第三虚拟金属，并且在平面图内设置在电感器内部;多个第四虚拟金属，形成在与多个第三部分相同的层中 虚拟金属并且在平面图中设置在电感器的外部，以及形成在与多个第三虚拟金属相同的层中并且被设置为与电感器重叠的多个第五虚拟金属。

公开(公告)号：US08907460B2

公开(公告)日：2014-12-09

申请号：US14012324

申请日：2013-08-28

Applicant: Renesas Electronics Corporation

Inventor： Takasuke Hashimoto ,  Shinichi Uchida ,  Yasutaka Nakashiba ,  Takatsugu Nemoto

IPC: H01L23/552 ,  H01L23/522 ,  H01L23/58 ,  H05K9/00

CPC classification number: H01L23/5225 ,  H01L23/5227 ,  H01L23/585 ,  H01L2924/0002 ,  H05K9/00 ,  H01L2924/00

Abstract: To suppress the noise caused by an inductor leaks to the outside, and also to be configured such that magnetic field intensity change reaches the inductor. An inductor surrounds an internal circuit in a planar view and also is coupled electrically to the internal circuit. The upper side of the inductor is covered by an upper shield part and the lower side of the inductor is covered by a lower shield part. The upper shield part is formed by the use of a multilayered wiring layer. The upper shield part has plural first openings. The first opening overlaps the inductor in the planar view.

Abstract translation: 为了抑制由电感器引起的噪声泄漏到外部，并且还被配置为使得磁场强度变化到达电感器。 电感器在平面视图中围绕内部电路，并且还与内部电路电连接。 电感器的上侧由上屏蔽部分覆盖，电感器的下侧由下屏蔽部分覆盖。 上部屏蔽部分通过使用多层布线层形成。 上部屏蔽部分具有多个第一开口。 第一个开口在平面视图中与电感器重叠。

公开(公告)号：US20140210046A1

公开(公告)日：2014-07-31

申请号：US14228987

申请日：2014-03-28

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Uchida

IPC: H01L23/66 ,  H01L23/64

CPC classification number: H01L23/5283 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/585 ,  H01L2223/6611 ,  H01L2924/0002 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate, and a multilayer wiring layer provided over the semiconductor substrate. The multilayer wiring layer includes an inductor wiring formed in one wiring layer, a plurality of first dummy metals formed in the same layer as the inductor and provided inside the inductor, a plurality of second dummy metals formed in a same layer as the inductor and provided outside the inductor, a plurality of third dummy metals formed in a layer lower than the one wiring layer including the inductor, and provided inside the inductor in a plan view, a plurality of fourth dummy metals formed in a same layer as the plurality of third dummy metals and provided outside the inductor in the plan view, and a plurality of fifth dummy metals formed in the same layer as the plurality of third dummy metals and provided to overlap with the inductor.

Abstract translation: 半导体器件包括半导体衬底和设置在半导体衬底上的多层布线层。 所述多层布线层包括形成在一个布线层中的电感器布线，与所述电感器形成在与所述电感器相同的层中并设置在所述电感器内的多个第一伪金属，形成在与所述电感器相同的层中的多个第二伪金属， 在电感器的外部，形成在比包括电感器的一个布线层低的层中的多个第三虚拟金属，并且在平面图内设置在电感器内部;多个第四虚拟金属，形成在与多个第三部分相同的层中 虚拟金属并且在平面图中设置在电感器的外部，以及形成在与多个第三虚拟金属相同的层中并且被设置为与电感器重叠的多个第五虚拟金属。

公开(公告)号：US11024566B2

公开(公告)日：2021-06-01

申请号：US16653127

申请日：2019-10-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi Uchida ,  Akio Ono ,  Shinichi Kuwabara ,  Yasutaka Nakashiba

IPC: H01L23/495 ,  H01L23/522 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/64

Abstract: A first semiconductor chip and a second semiconductor chip are stacked such that a first inductor and a second inductor face each other. An insulating sheet is disposed between the first semiconductor chip and the second semiconductor chip. The sealing member seals the first semiconductor chip, the second semiconductor chip, and the insulating sheet. The sealing member is disposed both between the insulating sheet and the first semiconductor chip and between the insulating sheet and the second semiconductor chip.

公开(公告)号：US10991653B2

公开(公告)日：2021-04-27

申请号：US16438018

申请日：2019-06-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi Uchida ,  Yasutaka Nakashiba

IPC: H01L21/00 ,  H01L23/522 ,  H01L49/02 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L23/528 ,  H01L21/84 ,  H01L27/12

Abstract: In a semiconductor device, a semiconductor substrate includes a bulk layer, a buried oxide layer provided in at least a partial region on the bulk layer, and a surface single crystal layer on the buried oxide layer. An inductor is provided above a main surface side of the semiconductor substrate on which the surface single crystal layer is disposed. To increase a Q value of the inductor, a ground shield is an impurity region formed in the bulk layer below the inductor and below the buried oxide layer.

公开(公告)号：US10446485B2

公开(公告)日：2019-10-15

申请号：US15858529

申请日：2017-12-29

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Uchida

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/58

Abstract: A semiconductor device includes: a plurality of first wires formed in a first layer and indicating fixed potentials; and an inductor formed in a second layer stacked on the first layer, and wiring widths of the first wires located within a range of a formation region of the inductor in a plan view among the plurality of first wires are formed narrower than wiring widths of the first wires located outside the range of the formation region of the inductor.