公开(公告)号：US07921836B2

公开(公告)日：2011-04-12

申请号：US12436806

申请日：2009-05-07

申请人： Khanh Tran

发明人： Khanh Tran

IPC分类号： F41B11/00

CPC分类号： F41B11/55 ,  F41A9/38 ,  F41B11/52

摘要： A paintball marker includes a main body and a dual feed adapter coupled to the main body. The dual feed adapter has a hollow interior, a top feed port and a bottom feed port. A top feed storage hopper is detachably connected to the dual feed adapter at the top feed port, and a bottom feed storage magazine is detachably connected to the dual feed adapter at the bottom feed port. A sleeve with an opening is rotatable within the dual feed adapter between a first position where the sleeve opening aligns with the top feed port for feeding therethrough a first group of paintballs from the hopper, and a second position where the sleeve opening aligns with the bottom feed port for feeding therethrough a second group of paintballs from the magazine.

摘要翻译： 彩弹标记器包括主体和耦合到主体的双馈进给适配器。 双进给适配器具有中空内部，顶部进料口和底部进料口。 顶部进料储存料斗在顶部进料口处可拆卸地连接到双进料适配器，并且底部进料存储盒可拆卸地连接到底部进料口处的双进料适配器。 具有开口的套筒可在双进给适配器内在第一位置和第二位置之间旋转，第一位置和第二位置之间，其中套筒开口与顶部进料口对准，用于从料斗通过第一组彩弹，以及第二位置，其中套筒开口与底部 馈送端口，用于从盒中馈送第二组彩弹。

公开(公告)号：US06607962B2

公开(公告)日：2003-08-19

申请号：US09925945

申请日：2001-08-09

申请人： Viktor Zekeriya ,  Khanh Tran

发明人： Viktor Zekeriya ,  Khanh Tran

IPC分类号： H01L2120

CPC分类号： H01L24/05 ,  H01L23/5228 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/1147 ,  H01L2224/13007 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method of forming a thin film resistor contact incorporates an etch-stop material to protect the underlying thin film resistor from a subsequent dry etching process to form a contact opening to the thin film resistor. More specifically, the method includes forming a thin film resistor, forming a first dielectric layer over the thin film resistor, forming a first opening through the first dielectric layer to expose an underlying portion of the thin film resistor, forming an etch-stop within the first opening of the first dielectric layer, forming a second dielectric layer over the etch-stop and the first dielectric layer, forming a second opening through the second dielectric layer to expose the underlying portion of the etch-stop, and forming a metal plug within the second contact opening, wherein the metal plug is in electrical contact with the thin film resistor by way of the etch-stop. Alternatively, in the case of an insulating etch-stop, the second opening through the dielectric layer is through the etch-stop, and forming a metal plug within the second contact opening, wherein the metal plug is in direct electrical contact with the thin film resistor.

摘要翻译： 形成薄膜电阻器触点的方法包括蚀刻停止材料，以保护下面的薄膜电阻器免受后来的干蚀刻工艺以形成对薄膜电阻器的接触开口。 更具体地，该方法包括形成薄膜电阻器，在薄膜电阻器上形成第一电介质层，形成穿过第一电介质层的第一开口以暴露薄膜电阻器的下面部分，在该薄膜电阻器的内部形成蚀刻停止 第一介电层的第一开口，在蚀刻停止层和第一介电层上方形成第二介电层，形成通过第二介电层的第二开口以暴露蚀刻停止层的下面部分，并在其内形成金属塞 第二接触开口，其中金属插塞通过蚀刻停止与薄膜电阻器电接触。 或者，在绝缘蚀刻停止的情况下，穿过介电层的第二开口通过蚀刻停止，并且在第二接触开口内形成金属插塞，其中金属插塞与薄膜直接电接触 电阻。

公开(公告)号：US06351013B1

公开(公告)日：2002-02-26

申请号：US09352339

申请日：1999-07-13

申请人： Scott Luning ,  David Wu ,  Khanh Tran

发明人： Scott Luning ,  David Wu ,  Khanh Tran

IPC分类号： H01L31062

CPC分类号： H01L29/6659 ,  H01L21/02134 ,  H01L21/02282 ,  H01L21/3124 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/66598 ,  Y10S257/90

摘要： The capacitance between the gate electrode and the source/drain regions of a semiconductor device is reduced by forming sub-spacers of a low dielectric constant (K) material at the corners of the gate electrode above the source/drain regions. Subsequently, insulating sidewall spacers are formed over the sub-spacers to shield-shallow source/drain regions from subsequent impurity implantations. The resulting semiconductor device exhibits reduced capacitance between the gate electrode and the source/drain regions, while maintaining circuit reliability.

摘要翻译： 通过在源极/漏极区域之上的栅电极的角部形成低介电常数（K）材料的子间隔物来减小半导体器件的栅电极和源/漏区之间的电容。 随后，在子间隔物之上形成绝缘侧壁间隔物以屏蔽浅源/漏区，从而避免随后的杂质注入。 所得到的半导体器件在保持电路可靠性的同时，在栅极电极和源极/漏极区域之间表现出减小的电容。

公开(公告)号：US06329718B1

公开(公告)日：2001-12-11

申请号：US09105775

申请日：1998-06-26

申请人： Minh Van Ngo ,  Paul R. Besser ,  Matthew Buynoski ,  John Caffall ,  Nick MacCrae ,  Richard J. Huang ,  Khanh Tran

发明人： Minh Van Ngo ,  Paul R. Besser ,  Matthew Buynoski ,  John Caffall ,  Nick MacCrae ,  Richard J. Huang ,  Khanh Tran

IPC分类号： H01L2348

CPC分类号： H01L21/7685 ,  H01L21/76837 ,  H01L21/76858 ,  H01L21/76885 ,  H01L23/53223 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for making 0.25 micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature, and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.

摘要翻译： 用于制造0.25微米半导体芯片的方法包括在线之间沉积层间电介质（ILD）之前退火金属互连线。 在退火期间，形成铝和钛的合金，其随后容积收缩，收缩被铝吸收。 因为合金在ILD沉积之前反应，所以当铝试图吸收合金的收缩时，铝不受ILD的约束。 因此，互连线中不希望的空隙形成的可能性降低。 在随后的ILD间隙填充沉积过程中，通过使用相对低的偏置功率来降低气相沉积温度，并且通过使用相对较低的源气体沉积流速来减少互连线上的流动引起的压缩应力，仍然进一步降低了不希望的空隙形成的可能性 在ILD形成期间。

公开(公告)号：US5582881A

公开(公告)日：1996-12-10

申请号：US602200

申请日：1996-02-16

申请人： Paul R. Besser ,  Raymond Lee ,  Khanh Tran

发明人： Paul R. Besser ,  Raymond Lee ,  Khanh Tran

IPC分类号： C23C14/06 ,  C23C14/16 ,  C23C14/56 ,  H05H1/24

CPC分类号： C23C14/165 ,  C23C14/0641 ,  C23C14/568

摘要： A single chamber of a vapor deposition system is used to deposit both Ti and TiN, subsequent to deposition of Al or Al alloy. Because such layers are deposited in the same chamber, the process requires fewer handling steps than the conventional process, thereby increasing throughput. Still further, only three physical vapor deposition chambers of the four of the apparatus are used, thereby allowing the fourth chamber to be used for other deposition.

摘要翻译： 在沉积Al或Al合金之后，使用单室蒸镀系统沉积Ti和TiN。 因为这样的层被沉积在相同的室中，所以该方法比常规方法需要较少的处理步骤，从而增加产量。 此外，仅使用四个设备中的三个物理气相沉积室，从而允许第四室用于其他沉积。

公开(公告)号：US10718591B2

公开(公告)日：2020-07-21

申请号：US16448004

申请日：2019-06-21

申请人： Khanh Tran

发明人： Khanh Tran

IPC分类号： F41B11/00 ,  F41B11/70 ,  F41B11/62

摘要： The present disclosure provides a foldable buttstock assembly for a pneumatic air gun. The foldable buttstock assembly has a foldable buttstock air fitting adapter connected to an air tank to a barrel unit of the pneumatic air gun. It also has an air channeling fitting to channel flow of the air gas. The pneumatic air gun can be operated while the air tank is in any position.

公开(公告)号：US20100178747A1

公开(公告)日：2010-07-15

申请号：US12352679

申请日：2009-01-13

申请人： Joseph Paul Ellul ,  Khanh Tran ,  Albert Bergemont

发明人： Joseph Paul Ellul ,  Khanh Tran ,  Albert Bergemont

IPC分类号： H01L21/02

CPC分类号： H01L25/50 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/81 ,  H01L25/0657 ,  H01L27/0805 ,  H01L28/91 ,  H01L29/66181 ,  H01L29/945 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/05552 ,  H01L2924/00

摘要： Passive, high density, 3d IC capacitor stacks and methods that provide the integration of capacitors and integrated circuits in a wafer to wafer bonding process that provides for the integration of capacitors formed on one wafer, alone or with active devices, with one or more integrated circuits on one or more additional wafers that may be stacked in accordance with the process. Wafer to wafer bonding is preferably by thermo-compression, with grinding and chemical mechanical polishing being used to simply aspects of the process of fabrication. Various features and alternate embodiments are disclosed.

摘要翻译： 被动的，高密度的3d IC电容器堆叠和方法，其提供电容器和集成电路在晶片到晶片接合工艺中的集成，其提供了在一个晶片上单独或与有源器件形成的电容集成，其中一个或多个集成 可以根据该过程堆叠的一个或多个另外的晶片上的电路。 晶圆接合的晶片优选通过热压缩，通过研磨和化学机械抛光仅用于制造工艺的方面。 公开了各种特征和替代实施例。

公开(公告)号：US07664982B2

公开(公告)日：2010-02-16

申请号：US11588441

申请日：2006-10-26

申请人： Lawton Chun-Hing Mue ,  Inderjit Singh Chohan ,  Khanh Tran

发明人： Lawton Chun-Hing Mue ,  Inderjit Singh Chohan ,  Khanh Tran

IPC分类号： G06F11/00

CPC分类号： G06F11/1451 ,  G06F11/1469

摘要： Methods and systems for storing recovery related information on a computer memory are described. One exemplary method comprises accessing a user input relating to a user selection of applications to be restored upon executing a recovery of the memory and storing on a recovery partition of the memory a recovery image corresponding to a user image on a user partition of the memory. The user image comprises the user selection of applications. Upon executing a recovery, the recovery image is copied to the user partition such that the user image is configured to correspond to the recovery image. The recovery image is derived from a set of applications that includes at least one un-installed application.

摘要翻译： 描述了用于在计算机存储器上存储恢复相关信息的方法和系统。 一个示例性方法包括：在执行存储器的恢复时访问与要恢复的应用程序的用户选择相关的用户输入，并且在存储器的恢复分区上存储与存储器的用户分区上的用户映像相对应的恢复图像。 用户图像包括用户对应用的选择。 在执行恢复时，将恢复图像复制到用户分区，使得用户图像被配置为对应于恢复图像。 恢复映像源自包括至少一个未安装应用程序的一组应用程序。

公开(公告)号：US06455098B2

公开(公告)日：2002-09-24

申请号：US09802692

申请日：2001-03-08

申请人： Khanh Tran ,  Tom Kelly ,  Arin Chang ,  Guy Mendez

发明人： Khanh Tran ,  Tom Kelly ,  Arin Chang ,  Guy Mendez

IPC分类号： B05D302

CPC分类号： H01L21/67751

摘要： A method and apparatus are described for transferring processing structures between first and second processing environments. The apparatus includes a first apparatus compartment configured to provide the first processing environment and a second apparatus compartment configured to provide the second processing environment. The apparatus is preferably configured for transferring wafer structures between the processing environments. The first and second processing environments are coupled together through a transfer passage that is opened and closed in order to isolate the wafer in a small transfer volume between the processing environments. Preferably, the transfer passage is opened and closed with first and second movable tables to create the small volume transfer cavity. In operation, the wafer is isolated within the small volume transfer cavity and the first and second tables are individually raised and lowered to expose the wafer to the first and second processing environments without opening the transfer passage between the first and second apparatus compartments. According to an embodiment of the invention, the apparatus is configured with a chemical delivery system that monitors the chemical composition or chemical concentration within the second apparatus compartment and supplies the appropriate quantity of chemical or chemicals to maintain a selected composition or concentration therein. According to a preferred embodiment the apparatus is configured for processing wafers coated with silicon-based materials to produce porous low-k coatings.

公开(公告)号：US06232221B1

公开(公告)日：2001-05-15

申请号：US09260001

申请日：1999-03-02

申请人： Khanh Tran ,  Sunil Mehta ,  Andre Stolmeijer

发明人： Khanh Tran ,  Sunil Mehta ,  Andre Stolmeijer

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： Borderless vias are formed by depositing a hard dielectric mask layer on the upper surface of a lower metal feature and forming sidewall spacers on the side surfaces of the metal feature and mask layer. A dielectric interlayer is deposited and a misaligned through-hole formed therein by etching. The dielectric material of the sidewall spacer and dielectric material of the dielectric interlayer are different. The etchant employed to form the through-hole exhibits a high selectivity with respect to the sidewall spacer material. The dielectric mask layer enables the formation of a sidewall spacer extending above the metal feature such that, after etching to form the misaligned through-hole, the sidewall spacer covers the side surface of the metal feature.

摘要翻译： 通过在下金属特征的上表面上沉积硬介电掩模层并在金属特征和掩模层的侧表面上形成侧壁间隔而形成无边界通孔。 沉积电介质中间层，通过蚀刻形成不对准的通孔。 电介质中间层的侧壁间隔物和电介质材料的电介质材料是不同的。 用于形成通孔的蚀刻剂相对于侧壁间隔物材料显示出高选择性。 电介质掩模层能够形成在金属特征之上延伸的侧壁间隔，使得在蚀刻以形成未对准的通孔之后，侧壁间隔物覆盖金属特征的侧表面。