公开(公告)号：US11037620B1

公开(公告)日：2021-06-15

申请号：US16916280

申请日：2020-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghak Song ,  Chanho Lee ,  Juchang Lee ,  Taemin Choi

IPC: G11C11/40 ,  G11C11/408 ,  G11C29/44 ,  G11C11/4094

Abstract: A memory device having fault detection functionality for improving functional safety and a control system including the memory device are provided. The memory device includes a first memory cell array configured to store input data and output the input data as output data and a second memory cell array configured to store bit values of a row address and a column address of the first memory cell array in which the input data is stored, and output the bit values of the row address and the column address as an internal row address and an internal column address. The row/column address designating a read operation may be compared to the internal row/column address, and an address comparison signal as a result of the comparison may be output. The address comparison signal may provide fault detection functionality for a data error of an automotive electronic system.

公开(公告)号：US20190206816A1

公开(公告)日：2019-07-04

申请号：US16151724

申请日：2018-10-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINCHAN AHN ,  Won-young Kim ,  Chanho Lee

IPC: H01L23/00

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a metal line layer on a semiconductor substrate, and a metal terminal on the metal line layer. The metal line layer includes metal lines, and a passivation layer having a non-planarized top surface including flat surfaces on the metal lines and a concave surface between the metal lines. The metal terminal is provided on the passivation layer. Opposite lateral surfaces of the metal terminal facing each other are provided on the flat surfaces of the passivation layer.

公开(公告)号：US10211070B2

公开(公告)日：2019-02-19

申请号：US15815032

申请日：2017-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Lee ,  Hyunsoo Chung ,  Hansung Ryu ,  InYoung Lee

IPC: H01L21/50 ,  H01L23/48 ,  H01L23/00 ,  H01L23/58 ,  H01L23/373 ,  H01L21/48 ,  H01L21/02

Abstract: A semiconductor device including a substrate, an insulating, layer on the substrate and including a trench, at least one via structure penetrating the substrate and protruding above a bottom surface of the trench, and a conductive structure surrounding the at least one via structure in the trench may be provided.

公开(公告)号：US20180158516A1

公开(公告)日：2018-06-07

申请号：US15706859

申请日：2017-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： INGYU PARK ,  Inhak Lee ,  Chanho Lee ,  Jaeseung Choi

IPC: G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C5/14 ,  G11C5/147 ,  G11C7/1096 ,  G11C11/412 ,  H01L27/1104

Abstract: A static random access memory device includes a plurality of memory cells arranged in rows and columns, a write driver configured to apply a bit line voltage corresponding to write data to a bit line extending in a column direction of the plurality of memory cells in a write operation, and a sub power line configured to transmit a cell driving voltage to the plurality of memory cells in the write operation and to extend in a direction parallel to the bit line, and includes a first node and a second node. The cell driving voltage is applied to the first node of the sub power line and the first node of the sub power line is aligned with an output node of the write driver in a row direction of the plurality of memory cells.

公开(公告)号：US09859204B2

公开(公告)日：2018-01-02

申请号：US15230889

申请日：2016-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong Soon Park ,  Hyunsoo Chung ,  Won-young Kim ,  Ae-nee Jang ,  Chanho Lee

IPC: H01L23/50 ,  H01L23/00

CPC classification number: H01L23/50 ,  H01L24/02 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06139 ,  H01L2224/06151 ,  H01L2224/06152 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/06159 ,  H01L2224/0616 ,  H01L2224/06165 ,  H01L2224/06169 ,  H01L2224/06177 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16227 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/0613

Abstract: Semiconductor devices with redistribution pads are disclosed. The semiconductor device includes a plurality of electric pads provided on a semiconductor substrate, and a plurality of redistribution pads electrically connected to the electric pads and an outer terminal. The plurality of redistribution pads includes a plurality of first redistribution pads constituting a transmission path for a first electrical signal and at least one second redistribution pad constituting a transmission path for a second electrical signal different from the first electrical signal. The first redistribution pads are arranged on the semiconductor substrate to form at least two rows, and the at least one second redistribution pad is disposed between the at least two rows of the first redistribution pads.

公开(公告)号：US20250014620A1

公开(公告)日：2025-01-09

申请号：US18754774

申请日：2024-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Lee ,  Junghak Song

IPC: G11C11/16

Abstract: A memory device may include a cell array including a first section and a second section that share a plurality of word lines comprising a first set of word lines and a second set of word lines, a first column decoder configured to select at least one bit line of a first set of bit lines connected to the first section, a second column decoder configured to select at least one bit line of a second set of bit lines connected to the second section, and a read circuit configured to output a data signal based on a comparison between an output of the first column decoder and an output of the second column decoder. The first section includes a plurality of first memory cells connected to at least one word line from the first set of word lines and configured to store bits of calibration data for calibrating the memory device, and the second section includes a plurality of second memory cells connected to the at least one word line and configured to store inverted bits of the calibration data.

公开(公告)号：US20240411971A1

公开(公告)日：2024-12-12

申请号：US18625456

申请日：2024-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Lee

IPC: G06F30/33 ,  G06F30/327

Abstract: A method of manufacturing a semiconductor device includes generating a target check code by performing target code generation computation on a target ROM code; generating first netlist data and first layout data of a semiconductor device including a mask ROM storing the target ROM code; inserting the target check code into the first netlist data; performing layout-versus-schematic (LVS) verification of the first netlist data and the first layout data, resulting in verified first netlist data; generating a final check code by performing the target code generation computation on a final ROM code of the mask ROM; determining whether the target check code stored in the first netlist data for which the LVS verification has been completed matches the final check code; and performing a mask tape-out operation (MTO) of the first layout data when the target check code matches the final check code.

公开(公告)号：US12080348B2

公开(公告)日：2024-09-03

申请号：US17820995

申请日：2022-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuwon Choi ,  Suk Youn ,  Chanho Lee ,  Taehyung Kim ,  Sangyeop Baeck ,  Inhak Lee

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A semiconductor device includes a substrate including a first memory cell, a second memory cell adjacent to the first memory cell in a first direction, and a comparator circuit adjacent to the first and second memory cells in a second direction intersecting the first direction; a true bit line and a complementary bit line electrically connected to the first and second memory cells and extending in the first direction from a first wiring layer on the substrate; a first power supply wiring on the first wiring layer, extending in the first direction between the true bit line and the complementary bit line and electrically connected to the first and second memory cells; first and second word lines extending in the second direction from a second wiring layer on the substrate different from the first wiring layer; first word line pads on the first wiring layer and electrically connecting the first memory cell to the first word line; second word line pads on the first wiring layer and electrically connecting the second memory cell to the second word line; and a first ground pad on the first wiring layer, electrically connected to the first and second memory cells, and in a same position as one of the first word line pads and one of the second word line pads in the second direction.

公开(公告)号：US20230178151A1

公开(公告)日：2023-06-08

申请号：US17820995

申请日：2022-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuwon Choi ,  Suk Youn ,  Chanho Lee ,  Taehyung Kim ,  Sangyeop Baeck ,  Inhak Lee

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A semiconductor device includes a substrate including a first memory cell, a second memory cell adjacent to the first memory cell in a first direction, and a comparator circuit adjacent to the first and second memory cells in a second direction intersecting the first direction; a true bit line and a complementary bit line electrically connected to the first and second memory cells and extending in the first direction from a first wiring layer on the substrate; a first power supply wiring on the first wiring layer, extending in the first direction between the true bit line and the complementary bit line and electrically connected to the first and second memory cells; first and second word lines extending in the second direction from a second wiring layer on the substrate different from the first wiring layer; first word line pads on the first wiring layer and electrically connecting the first memory cell to the first word line; second word line pads on the first wiring layer and electrically connecting the second memory cell to the second word line; and a first ground pad on the first wiring layer, electrically connected to the first and second memory cells, and in a same position as one of the first word line pads and one of the second word line pads in the second direction.

公开(公告)号：US11037894B2

公开(公告)日：2021-06-15

申请号：US16923406

申请日：2020-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinchan Ahn ,  Won-young Kim ,  Chanho Lee

IPC: H01L23/00 ,  H01L23/522

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a metal line layer on a semiconductor substrate, and a metal terminal on the metal line layer. The metal line layer includes metal lines, and a passivation layer having a non-planarized top surface including flat surfaces on the metal lines and a concave surface between the metal lines. The metal terminal is provided on the passivation layer. Opposite lateral surfaces of the metal terminal facing each other are provided on the flat surfaces of the passivation layer.