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    Hybrid DRAM array including dissimilar memory cells
    12.
    发明授权
    Hybrid DRAM array including dissimilar memory cells 有权

    公开(公告)号：US10223252B2

    公开(公告)日：2019-03-05

    申请号：US15496936

    申请日：2017-04-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng

    IPC: G06F12/02 ,  G11C8/12 ,  G11C8/14 ,  G11C8/16

    Abstract: A hybrid memory includes a plurality of tiles including a plurality of rows including a first row having a first type of memory cells and a second row having a second type of memory cells; a pair of bitline select signals including a bitline select signal and a bitline select bar signal that is an inverse of the bitline select signal; a wordline driver that is configured to receive an input data; a sense amplifier that is configured to output an output data; a write bitline coupled to the first row and the second row; a read bitline coupled to the first row and the second row; a wordline coupled to each of the plurality of rows; and a bitline that is coupled to the write bitline and the read bitline based on set values of the pair of bitline select signals.

    SYSTEMS AND METHODS FOR WRITE AND FLUSH SUPPORT IN HYBRID MEMORY
    14.
    发明申请
    SYSTEMS AND METHODS FOR WRITE AND FLUSH SUPPORT IN HYBRID MEMORY 审中-公开

    公开(公告)号：US20180329651A1

    公开(公告)日：2018-11-15

    申请号：US15669851

    申请日：2017-08-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Heehyun Nam ,  Youngjin Cho ,  Sun-Young Lim

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0685

    Abstract: A memory module includes a memory controller including: a host layer; a media layer coupled to a non-volatile memory; and a logic core coupled to the host layer, the media layer, and a volatile memory, the logic core storing a first write group table including a plurality of rows, and the logic core being configured to: receive a persistent write command including a cache line address and a write group identifier; receive data associated with the persistent write command; write the data to the volatile memory at the cache line address; store the cache line address in a selected buffer of a plurality of buffers in a second write group table, the selected buffer corresponding to the write group identifier; and update a row of the first write group table to identify locations of the selected buffer containing valid entries, the row corresponding to the write group identifier.

    Hybrid memory controller with command buffer for arbitrating access to volatile and non-volatile memories in a hybrid memory group
    15.
    发明授权
    Hybrid memory controller with command buffer for arbitrating access to volatile and non-volatile memories in a hybrid memory group 有权

    公开(公告)号：US10114560B2

    公开(公告)日：2018-10-30

    申请号：US15788501

    申请日：2017-10-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD

    Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Sun Young Lim ,  Indong Kim

    IPC: G06F13/00 ,  G06F3/06

    Abstract: A hybrid memory controller performs receiving first and second central processing unit (CPU) requests to write to/read from a hybrid memory group, identifying a volatile memory device and a non-volatile memory device as a first target and second target of the first and second CPU requests, respectively, by decoding and address mapping of the first and second CPU requests, queuing the first and second CPU requests in first and second buffers, respectively, generating, based on an arbitration policy, a first command corresponding to one of the first and second CPU requests to an associated one of the first and second targets, and generating a second command corresponding to another one of the first and second CPU requests to an associated another one of the first and second targets, and transmitting the first and second commands to respective ones of the volatile and non-volatile memory devices.

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