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11.发明申请APPARATUS AND METHOD FOR PREDICTING UPCOMING STAGE OF CAROTID STENOSIS 审中-公开用于预测CAROTID STENOSIS的最后阶段的装置和方法公开(公告)号：US20130274564A1
公开(公告)日：2013-10-17
申请号：US13837912
申请日：2013-03-15
发明人： Ha-Young Kim , Hye-Jin Kam , Sang-Hyun Yoo , Ji-Hyun Lee , Yoonho Choi , Mira Kang , Jeongeuy Park , Jidong Sung , Heeyoung Shin , Sungwon Cho , Soojin Cho
IPC分类号： A61B5/00 , A61B5/02 , A61B5/145 , A61B8/08 , A61B5/0205
CPC分类号： A61B5/7264 , A61B5/02007 , A61B5/0205 , A61B5/14546 , A61B5/7275 , A61B8/0891 , A61B8/5223 , G06F19/3456 , G16H50/30
摘要： An apparatus and a method predict an upcoming stage of carotid stenosis. The apparatus includes a receiving unit, a cluster determining unit, a risk factor score extracting unit, a prediction model storage unit, and a predicting unit. The method includes receiving a patient's medical test data relating to carotid stenosis; determining a cluster to which the patient's medical test data belong based on a gender of the patient; extracting from the patient's medical test data a risk factor score comprising a result of carotid stenosis ultrasonography; storing a plurality of prediction models used to predict an upcoming stage of carotid stenosis; and obtaining an outcome by applying a value indicating a stage of carotid stenosis corresponding to the result of carotid stenosis ultrasonography and the extracted risk factor score to the prediction model corresponding to the determined cluster among the plurality of prediction models.
摘要翻译： 一种装置和方法预测即将到来的颈动脉狭窄期。 该装置包括接收单元，群集确定单元，风险因子得分提取单元，预测模型存储单元和预测单元。 该方法包括接收患者关于颈动脉狭窄的医学检查数据; 基于患者的性别确定患者的医学检查数据所属的群集; 从患者的医学检验数据中提取包括颈动脉狭窄超声检查结果的危险因素评分; 存储用于预测即将到来的颈动脉狭窄期的多个预测模型; 通过将与颈动脉狭窄超声检查结果相对应的颈动脉狭窄阶段的值和所提取的风险因子得分应用于与所述多个预测模型中的所确定的群集对应的预测模型来获得结果。
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公开(公告)号：US10930675B2
公开(公告)日：2021-02-23
申请号：US16669639
申请日：2019-10-31
发明人： Jae-Woo Seo , Ki-Man Park , Ha-Young Kim , Junghwan Shin , Keunho Lee , Sungwe Cho
IPC分类号： H03K3/289 , H01L27/118 , H01L27/02 , H03K3/3562
摘要： Disclosed is a semiconductor device including a substrate with first and second regions adjacent to each other in a first direction, and first to third gate electrodes extending from the first region toward the second region. Each of the first and second regions includes a PMOSFET region and an NMOSFET region. The first to third gate electrodes extend in the first direction and are sequentially arranged in a second direction different from the first direction. The first and third gate electrodes are supplied with a first signal. The second gate electrode is supplied with a second signal that is an inverted signal of the first signal. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gates are aligned and connected with each other in the first direction.
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公开(公告)号：US10050058B2
公开(公告)日：2018-08-14
申请号：US15282206
申请日：2016-09-30
发明人： Taejoong Song , Ha-Young Kim , Jung-Ho Do , Sanghoon Baek , Jinyoung Lim , Kwangok Jeong
IPC分类号： H01L21/8238 , H01L27/118 , G06F17/50 , G03F1/36 , H01L21/66 , H01L27/02 , H01L27/092 , H01L27/11582
摘要： A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.
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公开(公告)号：US09779198B2
公开(公告)日：2017-10-03
申请号：US14832307
申请日：2015-08-21
发明人： Daekwon Kang , Donggyun Kim , Jaeseok Yang , Jiyoung Jung , Chunghee Kim , Ha-Young Kim , Sungkeun Park , Younggook Park , Myungsoo Jang , Jintae Kim
CPC分类号： G06F17/5072 , G03F1/36 , G03F1/70 , G06F17/5068 , G06F17/5081
摘要： A method can include separating a design area of a substrate for a semiconductor integrated circuit (IC) into cell blocks, where a distance between adjacent ones of the cell blocks can be greater than or equal to a minimum distance defined by a design rule for the semiconductor integrated circuit to provide separated cell blocks, designing a layout for the semiconductor IC in the separated cell blocks, and individually coloring the layout of each of the separated cell blocks.
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公开(公告)号：US09508167B2
公开(公告)日：2016-11-29
申请号：US14176301
申请日：2014-02-10
发明人： Ha-Young Kim , Hyoung-Min Park , Haesun Park , Jae-Gul Choo
CPC分类号： G06T11/206 , G06T19/00
摘要： A method and an apparatus are provided to visualize high-dimensional data. The method includes primarily visualizing the high-dimensional data at a dimension lower than the high-dimensional data to obtain a primarily-visualized image. The method also includes secondarily visualizing the high-dimensional data in an area of the primarily-visualized image at a dimension higher than the primarily-visualized image to obtain a secondarily-visualized image.
摘要翻译： 提供了一种可视化高维数据的方法和装置。 该方法主要包括在低于高维数据的维度上可视化高维数据以获得主要可视化图像。 该方法还包括以高于主要可视化图像的维度将主要可视化图像的区域中的高维数据二次可视化以获得二次可视化图像。
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16.发明申请APPARATUS AND METHOD FOR PREDICTING POTENTIAL CHANGE OF CORONARY ARTERY CALCIFICATION (CAC) LEVEL 有权用于预测冠状动脉计算（CAC）水平的潜在变化的装置和方法公开(公告)号：US20130275347A1
公开(公告)日：2013-10-17
申请号：US13835855
申请日：2013-03-15
发明人： Ji-Hyun Lee , Hye-Jin Kam , Ha-Young Kim , Sang-Hyun Yoo , Yoonho Choi , Mira Kang , Jeongeuy Park , Jidong Sung , Heeyoung Shin , Sungwon Cho , Soojin Cho
IPC分类号： G06N99/00
CPC分类号： G06N99/005 , G06F19/00 , G16H50/20 , G16H50/30
摘要： An apparatus and a method predict a patient's potential change of Coronary Artery Calcification (CAC) level using various risk factors including a Coronary Artery Calcification Score (CACS). The apparatus includes a receiving unit, a cluster determining unit, a risk factor score extracting unit, a prediction model storage unit, a prediction model learning unit, and a predicting unit, and the method includes a receiving process, a risk factor score extracting process, and an operation performing process.
摘要翻译： 一种装置和方法使用包括冠状动脉钙化评分（CACS）在内的各种危险因素来预测患者冠状动脉钙化（CAC）水平的潜在变化。 该装置包括接收单元，群集确定单元，风险因子得分提取单元，预测模型存储单元，预测模型学习单元和预测单元，并且该方法包括接收处理，风险因子得分提取处理 ，以及操作执行处理。
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17.发明申请APPARATUS AND METHOD FOR PREDICTING POTENTIAL DEGREE OF CORONARY ARTERY CALCIFICATION (CAC) RISK 审中-公开用于预测冠状动脉计算（CAC）风险潜在程度的装置和方法公开(公告)号：US20130275154A1
公开(公告)日：2013-10-17
申请号：US13834150
申请日：2013-03-15
发明人： Hye-Jin Kam , Ha-Young Kim , Sang-Hyun Yoo , Ji-Hyun Lee , Yoonho Choi , Mira Kang , Jeongeuy Park , Jidong Sung , Heeyoung Shin , Sungwon Cho , Soojin Cho
摘要： A method of predicting a potential degree of Coronary Artery Calcification (CAC) risk includes receiving a patient's medical test data relating to CAC; determining a cluster to which the patient's medical test data belong based on an age of the patient; extracting a risk factor score including at least two Coronary Artery Calcification Scores (CACSs) from the medical test data; storing a plurality of prediction models used for predicting a potential degree of CAC risk; and predicting a potential degree of CAC risk at a specific point in time by applying a CACS growth rate of the patient's medical test data calculated using the at least two CACSs of the patient's medical test data and the extracted risk factor score to a prediction model corresponding to the determined cluster to which the patient's medical test data belong among the plurality of prediction models.
摘要翻译： 预测冠状动脉钙化（CAC）风险潜在程度的方法包括接收患者与CAC有关的医学检验数据; 基于患者的年龄确定患者的医学测试数据所属的群集; 从医疗测试数据中提取包括至少两个冠状动脉钙化积分（CACS）的风险因子得分; 存储用于预测潜在的CAC风险程度的多个预测模型; 并且通过将使用患者医疗测试数据的至少两个CACS计算的患者的医疗测试数据的CACS增长率和所提取的危险因素得分应用到对应的预测模型来预测在特定时间点的CAC风险的潜在程度 到患者的医学测试数据属于多个预测模型中的确定的群集。
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公开(公告)号：US11287474B2
公开(公告)日：2022-03-29
申请号：US16552109
申请日：2019-08-27
发明人： Ha-Young Kim , Sung-We Cho , Dal-Hee Lee , Jae-Ha Lee
IPC分类号： G01R31/3185 , H03K3/3562
摘要： A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop is configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.
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公开(公告)号：US11201172B2
公开(公告)日：2021-12-14
申请号：US17153939
申请日：2021-01-21
发明人： Jae-Woo Seo , Ki-Man Park , Ha-Young Kim , Junghwan Shin , Keunho Lee , Sungwe Cho
IPC分类号： H03K3/356 , H01L27/118 , H01L27/02 , H03K3/3562
摘要： Disclosed is a semiconductor device including a substrate with first and second regions adjacent to each other in a first direction, and first to third gate electrodes extending from the first region toward the second region. Each of the first and second regions includes a PMOSFET region and an NMOSFET region. The first to third gate electrodes extend in the first direction and are sequentially arranged in a second direction different from the first direction. The first and third gate electrodes are supplied with a first signal. The second gate electrode is supplied with a second signal that is an inverted signal of the first signal. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gates are aligned and connected with each other in the first direction.
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公开(公告)号：US11043428B2
公开(公告)日：2021-06-22
申请号：US16450383
申请日：2019-06-24
发明人： Ha-Young Kim , Jin Tae Kim , Jae-Woo Seo , Dong-yeon Heo
IPC分类号： H01L27/02 , H01L21/8234 , G06F30/392 , H01L21/768 , G06F30/398 , H01L21/8238 , H01L27/06
摘要： A method of manufacturing a semiconductor device includes configuring a layout pattern; and forming conductive lines corresponding to the layout pattern on a substrate, wherein configuring the layout pattern includes: arranging pre-conductive patterns and post-conductive patterns for a first logic cell, a second logic cell, and a third logic cell; rearranging the pre-conductive patterns and the post-conductive patterns so that two conductive patterns that are adjacent to a boundary between two adjacent logic cells from among the first logic cell, the second logic cell, and the third logic cell are formed by different photolithography processes; and arranging conductive patterns for a dummy cell arranged between the second logic cell and the third logic cell.
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