公开(公告)号：US08982618B2

公开(公告)日：2015-03-17

申请号：US13795750

申请日：2013-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hyun Joo ,  Il-Han Park ,  Ki-Whan Song

IPC: G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/10

CPC classification number: G11C16/3418 ,  G11C11/5628 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26

Abstract: A nonvolatile memory device comprises a nonvolatile memory chip comprising a static latch, first and second dynamic latches that receive the data stored in the static latch through a floating node, and a memory cell configured to store multi-bit data. The nonvolatile memory device performs a refresh operation on the first dynamic latch where externally supplied first single bit data is stored in the first dynamic latch, performs a refresh operation on the second dynamic latch where externally supplied second single bit data is stored in the second dynamic latch, and programs the memory cell using the data stored in the first and second dynamic latches after the first and second single bit data are stored in the respective first and second dynamic latches.

Abstract translation: 非易失性存储器件包括非易失性存储器芯片，其包括静态锁存器，通过浮动节点接收存储在静态锁存器中的数据的第一和第二动态锁存器以及被配置为存储多位数据的存储器单元。 非易失性存储器件对第一动态锁存器执行刷新操作，其中外部提供的第一单位数据被存储在第一动态锁存器中，对外部提供的第二单位数据存储在第二动态锁存器中的第二动态锁存器执行刷新操作 在第一和第二单个位数据存储在相应的第一和第二动态锁存器中之后，使用存储在第一和第二动态锁存器中的数据对存储器单元进行锁存和编程。

公开(公告)号：US12112056B2

公开(公告)日：2024-10-08

申请号：US18202692

申请日：2023-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hyun Joo

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/14 ,  G11C16/16

CPC classification number: G06F3/0652 ,  G06F3/0604 ,  G06F3/0679 ,  G11C11/5635 ,  G11C16/14 ,  G11C16/16 ,  G11C2211/5642

Abstract: In some embodiments, a non-volatile memory device includes a control logic circuit configured to generate a program signal and an erase signal based on control signals, a voltage generator configured to generate a program voltage and an erase voltage based on the program signal and the erase signal, a memory cell array including a memory cell, a string select transistor coupled to the memory cell, a bit-line coupled to the string select transistor, and a string select line coupled to the string select transistor, and a page buffer circuit coupled to the bit-line, and including a first precharge transistor that is configured to operate based on the program signal and the erase signal. The first precharge transistor is configured to apply the program voltage and the erase voltage to the bit-line in response to the program signal and the erase signal, respectively.

公开(公告)号：US20180373592A1

公开(公告)日：2018-12-27

申请号：US16121072

申请日：2018-09-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Woo Im ,  Sang-Hyun Joo

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G11C29/52

Abstract: A memory cell array includes memory cells that are formed in vertical channels extended in a vertical direction with respect to a substrate. The vertical channels are arranged in a zigzag manner in parallel to the first direction. A read-write circuit is connected to the memory cells via bit lines. An address decoder decodes an address to provide decoded address signals to the read-write, circuit. The memory cells include outer cells and inner cells. A distance between one of the outer cells and a common source node is smaller than a distance between one of the inner cells and the common source node. Data of the memory cells are distributed among ECC sectors and a data input-output order of the memory cells is arranged such that each ECC sector has substantially the same number of the outer cells and the inner cells. Each ECC sector corresponds to an ECC operation unit.

公开(公告)号：US09892795B2

公开(公告)日：2018-02-13

申请号：US15350134

申请日：2016-11-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hyun Joo ,  KeeHo Jung

IPC: G11C16/06 ,  G11C16/26 ,  G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3445

Abstract: A nonvolatile memory device includes a memory cell array, a row decoder, and page buffer, and control logic. The memory cell array includes cell strings connected to select lines. Each select line is connected to two or more cell strings, each cell string includes memory cells connected to a plurality of word lines, and a select transistor is connected to a corresponding one of the select lines. The row decoder sequentially selects the select lines in a read operation. A page buffer obtains a read result of the two or more cell strings when a corresponding select line is selected and accumulates read results of the cell strings when the select lines are sequentially selected. The control logic controls a subsequent operation based on the accumulated read results.

公开(公告)号：US09779833B2

公开(公告)日：2017-10-03

申请号：US15291676

申请日：2016-10-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hyun Joo ,  Jae-Woo Im

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3495 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459

Abstract: A method of programming a flash memory device, which is a nonvolatile memory device including a plurality of pages, includes executing an Nth program loop of a program operation by applying an Nth selected program voltage to a selected word line from among the plurality of pages, and performing a program verify operation by applying a program verify voltage to the selected word line, counting the number of memory cells having a threshold voltage which is greater than or equal to the program verify voltage, from among memory cells connected to the selected word line, generating a program voltage revision value based on a result of the counting and an operational condition of the Nth program loop, and adding the program voltage revision value to an Mth preset program voltage of an Mth program loop executed after the Nth program loop where M>N.

公开(公告)号：US09747997B2

公开(公告)日：2017-08-29

申请号：US15292417

申请日：2016-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Jun Lee ,  Sang-Hyun Joo

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  G11C16/16

CPC classification number: G11C16/3495 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12005 ,  G11C29/26 ,  G11C29/50004 ,  G11C2029/0409 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: A method of operating a non-volatile memory device includes selecting a first select transistor from among a plurality of select transistors included in a NAND string, and performing a check operation on a first threshold voltage of the first select transistor. The check operation includes comparing the first threshold voltage with a first lower-limit reference voltage level, and performing a program operation on the first select transistor when the first threshold voltage is lower than the first lower-limit reference voltage level. When the first threshold voltage is equal to or higher than the first lower-limit reference voltage level, the check operation on the first threshold voltage is ended.

公开(公告)号：US08958251B2

公开(公告)日：2015-02-17

申请号：US13913710

申请日：2013-06-10

Applicant: Samsung Electronics Co., Ltd

Inventor： Ohsuk Kwon ,  Sang-Hyun Joo ,  HyeongJun Kim ,  Kitae Park ,  Seung-Hwan Shin

IPC: G11C16/06 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/24 ,  G11C16/3459

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a page buffer circuit connected with the memory cell array via a plurality of bit lines and configured to selectively pre-charge the plurality of bit lines, and control logic configured to control the page buffer circuit such that a pre-charge voltage is applied to selected bit lines of the plurality of bit lines during a first time at a read operation and such that a pre-charge voltage is applied to selected bit lines of the plurality of bit lines during a second time different from the first time at a verification read operation. The second time is determined on the basis of the number of selected bit lines of the plurality of bit lines at the verification read operation.

Abstract translation: 非易失性存储器件包括包括多个存储器单元的存储单元阵列，经由多个位线与存储单元阵列连接并被配置为选择性地预充电多个位线的页缓冲器电路，以及配置为 控制页面缓冲器电路，使得在读取操作的第一时间期间将预充电电压施加到多个位线的选定位线，并且使得预充电电压被施加到多个位线中的选定位线 在第二时间不同于在验证读取操作的第一时间的位线。 基于在验证读取操作中的多个位线的选定位线的数量来确定第二次。

公开(公告)号：US12020759B2

公开(公告)日：2024-06-25

申请号：US17878019

申请日：2022-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Ho Seo ,  Juwon Lee ,  Suk-Eun Kang ,  Dogyeong Lee ,  Youngwook Jeong ,  Sang-Hyun Joo

IPC: G11C16/34 ,  G06N3/08 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24

CPC classification number: G11C16/3459 ,  G06N3/08 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/3495

Abstract: An operation method of a nonvolatile memory device includes performing a 1-stage program step and a 1-stage verify step on a first word line, storing a first time stamp, performing the 1-stage program step and the 1-stage verify step on a second word line, storing a second time stamp, calculating a delay time based on the first time stamp and the second time stamp, determining whether the delay time is greater than a threshold value, adjusting at least one 2-stage verify voltage associated with the first word line from a first voltage level to a second voltage level based on the delay time, and performing a 2-stage program step and a 2-stage verify step on the first word line. A level of the at least one 1-stage verify voltage is lower than the second voltage level, and the second voltage level is lower than the first voltage level.

公开(公告)号：US11462271B2

公开(公告)日：2022-10-04

申请号：US17126933

申请日：2020-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hak Yun ,  Jae Woo Im ,  Sang-Hyun Joo

IPC: G06F12/02 ,  G06F3/06 ,  G11C16/04 ,  G11C16/08 ,  G11C7/12 ,  G11C8/08 ,  G11C11/4074

Abstract: A nonvolatile memory device and an operating method are provided. The nonvolatile memory device includes a memory cell array including a plurality of planes, each plane including a plurality of memory blocks, an address decoder connected to the memory cell array, a voltage generator configured to apply an operating voltage to the address decoder, a page buffer circuit including page buffers corresponding to each of the planes, a data input/output circuit connected to the page buffer circuit configured to input and output data and a control unit configured to control the operation of the address decoder, the voltage generator, the page buffer circuit, and the data input/output circuit, wherein the control unit is configured to operate in a multi-operation or a single operation by checking whether a memory block of an access address is a bad block.

公开(公告)号：US10067825B2

公开(公告)日：2018-09-04

申请号：US15061349

申请日：2016-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Woo Im ,  Sang-Hyun Joo

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

Abstract: A memory cell array includes memory cells that are formed in vertical channels extended in a vertical direction with respect to a substrate. The vertical channels are arranged in a zig-zag manner in parallel to the first direction. A read-write circuit is connected to the memory cells via bit lines. An address decoder decodes an address to provide decoded address signals to the read-write circuit. The memory cells include outer cells and inner cells. A distance between one of the outer cells and a common source node is smaller than a distance between one of the inner cells and the common source node. Data of the memory cells are distributed among ECC sectors and a data input-output order of the memory cells is arranged such that each ECC sector has substantially the same number of the outer cells and the inner cells. Each ECC sector corresponds to an ECC operation unit.