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    Methods for fabricating semiconductor devices
    11.
    发明授权
    Methods for fabricating semiconductor devices 有权
    制造半导体器件的方法

    公开(公告)号：US09287300B2

    公开(公告)日：2016-03-15

    申请号：US14569980

    申请日：2014-12-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eunjung Kim ,  Yong Kwan Kim ,  Jemin Park ,  Semyeong Jang ,  Sangyeon Han ,  Yoosang Hwang

    IPC: H01L21/311 ,  H01L29/06 ,  H01L27/12 ,  H01L21/768

    CPC classification number: H01L27/1288 ,  H01L21/7688 ,  H01L27/10814 ,  H01L27/10891

    Abstract: The present inventive concepts provide methods for fabricating semiconductor devices. The method may comprise providing a substrate, stacking a conductive layer and a lower mask layer on the substrate, forming a plurality of hardmask layers each having an island shape on the lower mask layer, forming a plurality of upper mask patterns having island shapes arranged to expose portions of the lower mask layer, etching the exposed portions of the lower mask layer to expose portions of the conductive layer, and etching the exposed portions of the conductive layer to form a plurality of contact holes each exposing a portion of the substrate.

    Abstract translation: 本发明构思提供了制造半导体器件的方法。 该方法可以包括提供衬底，在衬底上堆叠导电层和下掩模层，在下掩模层上形成各自具有岛状的多个硬掩模层，形成具有岛形的多个上掩模图案，其布置成 暴露下掩模层的部分，蚀刻下掩模层的暴露部分以暴露导电层的部分，并且蚀刻导电层的暴露部分以形成多个接触孔，每个接触孔暴露衬底的一部分。

    Three-dimensional semiconductor memory device and a method of manufacturing the same
    12.
    发明授权
    Three-dimensional semiconductor memory device and a method of manufacturing the same 有权

    公开(公告)号：US12156401B2

    公开(公告)日：2024-11-26

    申请号：US17477634

    申请日：2021-09-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Joongchan Shin ,  Byeungmoo Kang ,  Sangyeon Han

    IPC: H10B41/27 ,  G11C5/06 ,  H01L23/538 ,  H10B43/27

    Abstract: A three-dimensional (3D) semiconductor memory device including: stack structures spaced apart from each other on a semiconductor substrate, wherein each of the stack structures includes interlayer insulating layers and semiconductor patterns alternately stacked on the semiconductor substrate; conductive patterns provided between the interlayer insulating layers vertically adjacent to each other and connected to the semiconductor patterns; and a protective structure covering a top surface of the semiconductor substrate between the stack structures, wherein a top surface of the protective structure is located between a top surface and a bottom surface of a lowermost interlayer insulating layer of the interlayer insulating layers.

    Semiconductor memory device
    14.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11751378B2

    公开(公告)日：2023-09-05

    申请号：US17369320

    申请日：2021-07-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyungeun Choi ,  Kiseok Lee ,  Seungjae Jung ,  Joongchan Shin ,  Taehyun An ,  Moonyoung Jeong ,  Sangyeon Han

    IPC: H10B12/00 ,  H01L29/08

    CPC classification number: H10B12/30 ,  H01L29/0847 ,  H10B12/03 ,  H10B12/05

    Abstract: A semiconductor memory device includes: a bit line extending on a substrate in a vertical direction; a transistor body part including a first source-drain region, a monocrystalline channel layer, and a second source-drain region that are sequentially arranged in a first horizontal direction and connected to the bit line; gate electrode layers extending in a second horizontal direction that is orthogonal to the first horizontal direction, with a gate dielectric layer between the gate electrode layers and the monocrystalline channel layer, and covering upper and lower surfaces of the monocrystalline channel layer; and a cell capacitor including a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer at a side of the transistor body that is opposite to the bit line in the first horizontal direction and is connected to the second source-drain region.

    Semiconductor devices having buried gates
    15.
    发明授权
    Semiconductor devices having buried gates 有权

    公开(公告)号：US11626409B2

    公开(公告)日：2023-04-11

    申请号：US17318563

    申请日：2021-05-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Huijung Kim ,  Minwoo Kwon ,  Sangyeon Han ,  Sangwon Kim ,  Junsoo Kim ,  Hyeonjin Shin ,  Eunkyu Lee

    IPC: H01L27/108 ,  H01L29/423 ,  H01L29/78

    Abstract: A semiconductor device includes a substrate including an active region, a gate structure disposed in a gate trench in the substrate, a bit line disposed on the substrate and electrically connected to the active region on one side of the gate structure, and a capacitor disposed on the bit line and electrically connected to the active region on another side of the gate structure. The gate structure includes a gate dielectric layer disposed on bottom and inner side surfaces of the gate trench, a conductive layer disposed on the gate dielectric layer in a lower portion of the gate trench, sidewall insulating layers disposed on the gate dielectric layer, on an upper surface of the conductive layer, a graphene conductive layer disposed on the conductive layer, and a buried insulating layer disposed between the sidewall insulating layers on the graphene conductive layer.

    Three-dimensional semiconductor memory device
    16.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US11502084B2

    公开(公告)日：2022-11-15

    申请号：US16986367

    申请日：2020-08-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Joongchan Shin ,  Changkyu Kim ,  Hui-Jung Kim ,  Iljae Shin ,  Taehyun An ,  Kiseok Lee ,  Eunju Cho ,  Hyungeun Choi ,  Sung-Min Park ,  Ahram Lee ,  Sangyeon Han ,  Yoosang Hwang

    IPC: H01L27/108 ,  H01L23/528 ,  H01L21/822

    Abstract: A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME
    18.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220093626A1

    公开(公告)日：2022-03-24

    申请号：US17477634

    申请日：2021-09-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Joongchan Shin ,  Byeungmoo Kang ,  Sangyeon Han

    IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  H01L23/538

    Abstract: A three-dimensional (3D) semiconductor memory device including: stack structures spaced apart from each other on a semiconductor substrate, wherein each of the stack structures includes interlayer insulating layers and semiconductor patterns alternately stacked on the semiconductor substrate; conductive patterns provided between the interlayer insulating layers vertically adjacent to each other and connected to the semiconductor patterns; and a protective structure covering a top surface of the semiconductor substrate between the stack structures, wherein a top surface of the protective structure is located between a top surface and a bottom surface of a lowermost interlayer insulating layer of the interlayer insulating layers.

    Semiconductor memory device and method of fabricating the same
    19.
    发明授权
    Semiconductor memory device and method of fabricating the same 有权

    公开(公告)号：US10665592B2

    公开(公告)日：2020-05-26

    申请号：US16108786

    申请日：2018-08-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jungwoo Song ,  Kwangmin Kim ,  Jun Ho Lee ,  Hyuckjin Kang ,  Yong Kwan Kim ,  Sangyeon Han ,  Seguen Park

    IPC: H01L29/06 ,  H01L27/108 ,  H01L23/532 ,  H01L27/24 ,  H01L27/22

    Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    20.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20190164975A1

    公开(公告)日：2019-05-30

    申请号：US16108786

    申请日：2018-08-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JUNGWOO SONG ,  Kwangmin Kim ,  Jun Ho Lee ,  Hyuckjin Kang ,  Yong Kwan Kim ,  Sangyeon Han ,  Seguen Park

    IPC: H01L27/108 ,  H01L23/532 ,  H01L29/06

    Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.

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