公开(公告)号：US12284066B2

公开(公告)日：2025-04-22

申请号：US17398381

申请日：2021-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yangsoo Kwon ,  Joonsung Kim ,  Jinwoo Oh ,  Yongin Choi

IPC: H04L27/26 ,  H04W4/40 ,  H04W72/20 ,  H04W92/10

Abstract: An apparatus and a method for effectively mapping a reference signal for vehicle-to-everything (V2X) communication in a wireless communication system are provided. A transmission terminal performing the V2X communication includes a processor generating sidelink control information (SCI) and a transceiver transmitting the generated SCI to a reception terminal through a physical sidelink control channel (PSCCH) and a physical sidelink shared channel (PSSCH). A decision on whether to allocate a demodulation reference signal (DMRS) of the PSSCH and the PSCCH to the same orthogonal frequency division multiplexing (OFDM) symbol is made based on a number of subchannels and at least one sized thereof.

公开(公告)号：US12176262B2

公开(公告)日：2024-12-24

申请号：US18475926

申请日：2023-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunseok Cho ,  Minjeong Gu ,  Joonsung Kim ,  Jaehoon Choi

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L25/065 ,  H01L25/18

Abstract: A method of manufacturing a semiconductor package is provided and includes: forming a lower redistribution structure, the lower redistribution structure including lower redistribution patterns having lower connection pads; forming an upper redistribution structure on a boundary surface of the lower redistribution structure, the upper redistribution structure including upper redistribution patterns having upper connection pads electrically connected to the lower connection pads; forming openings exposing at least a portion of each of the lower connection pads; disposing an interposer substrate, including the lower redistribution structure and the upper redistribution structure, on a base substrate, the lower connection pads of the interposer substrate electrically connected to wiring patterns of the base substrate through lower connection bumps disposed on the openings; and disposing at least one of semiconductor chips, including connection pads, on the interposer substrate, the connection pads electrically connected to the upper connection pads through upper connection bumps.

公开(公告)号：US12062617B2

公开(公告)日：2024-08-13

申请号：US17562127

申请日：2021-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonsung Kim

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/34 ,  H01L23/522

CPC classification number: H01L23/5383 ,  H01L23/3121 ,  H01L23/34 ,  H01L23/5226 ,  H01L23/5386 ,  H01L24/08 ,  H01L23/3171 ,  H01L2224/08235

Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor substrate and a first chip pad on a first bottom surface of the first semiconductor substrate, a second semiconductor chip including a second semiconductor substrate and a second chip pad on a second top surface of the second semiconductor substrate, a lower redistribution structure provided under the first semiconductor chip and the second semiconductor chip, the lower redistribution structure including a lower redistribution pattern, the lower redistribution pattern including a first lower redistribution via pattern contacting the first chip pad, a molding layer covering the first semiconductor chip and the second semiconductor chip, an upper redistribution structure including an upper redistribution pattern, the upper redistribution pattern including a first upper redistribution via pattern connected to the second chip pad, and a conductive connection structure electrically connecting the lower redistribution pattern to the upper redistribution pattern.

公开(公告)号：US20240065002A1

公开(公告)日：2024-02-22

申请号：US18231341

申请日：2023-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyu Kim ,  Joonsung Kim ,  Inhyung Song ,  Yeonho Jang

IPC: H10B80/00 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

CPC classification number: H10B80/00 ,  H01L25/18 ,  H01L24/20 ,  H01L25/50 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/19 ,  H01L2224/96 ,  H01L2224/214 ,  H01L2924/0105 ,  H01L2924/01049 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0103 ,  H01L2924/01082 ,  H01L24/32 ,  H01L2224/32145 ,  H01L24/33 ,  H01L2224/33181 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/17181 ,  H01L24/16 ,  H01L24/17 ,  H01L24/05 ,  H01L24/06 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/16145

Abstract: A semiconductor device including a first lower buffer chip, an upper buffer chip disposed on an upper surface of the first lower buffer chip, a plurality of conductive posts spaced apart from the first lower buffer chip and disposed on a lower surface of the upper buffer chip, and a first memory chip stack structure disposed on the upper buffer chip and including a plurality of first memory chips.

公开(公告)号：US20230187424A1

公开(公告)日：2023-06-15

申请号：US17862482

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonsung Kim ,  Seokwon Lee

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/13 ,  H01L49/02

CPC classification number: H01L25/16 ,  H01L24/08 ,  H01L24/16 ,  H01L23/49838 ,  H01L23/5386 ,  H01L23/13 ,  H01L28/90 ,  H01L25/162 ,  H01L2924/3511 ,  H01L2924/1438 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1431 ,  H01L24/48 ,  H01L2224/48225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/19041 ,  H01L2224/08146 ,  H01L2224/08225 ,  H01L2224/08265 ,  H01L2924/3011 ,  H01L23/49816 ,  H01L23/49833 ,  H01L2924/182

Abstract: A fan-out semiconductor package includes: a package body including a fan-in area corresponding to a through-hole located therein, a fan-out area surrounding the fan-in area, and a body interconnect structure arranged in the package body corresponding to the fan-out area; a fan-in chip structure located in the through-hole, the fan-in chip structure comprising a first chip, a capacitor chip arranged to be apart from the first chip, and a second chip disposed on both the first chip and the capacitor chip; a redistribution structure arranged on a bottom surface of the package body and a bottom surface of the fan-in chip structure and including a redistribution element extending to the fan-out area; and an interconnect via arranged on a top surface of the package body and electrically connected to the redistribution element in the fan-out area.

公开(公告)号：US11503569B2

公开(公告)日：2022-11-15

申请号：US17166111

申请日：2021-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongin Choi ,  Yangsoo Kwon ,  Joonsung Kim ,  Jinwoo Oh

IPC: H04W4/40 ,  H04B17/318 ,  H04B17/345 ,  H04L1/18 ,  H04W72/02 ,  H04B17/336 ,  H04L5/00 ,  H04W24/10 ,  H04W72/04

Abstract: An operating method of a terminal configured to perform vehicle-to-everything (V2X) communication in a wireless communication system, including signaling a maximum physical sidelink feedback channel (PSFCH) receiving capability to a base station; and receiving a wireless signal transmitted from the base station based on the maximum PSFCH receiving capability, wherein the maximum PSFCH receiving capability is a maximum number of PSFCHs receivable during one time transmission interval (TTI).

公开(公告)号：US20210183762A1

公开(公告)日：2021-06-17

申请号：US17022718

申请日：2020-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonsung Kim ,  Khaile Kim

IPC: H01L23/528 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: A fan-out semiconductor package includes a frame substrate having a through hole therein, a semiconductor chip in the through hole, wherein the semiconductor chip includes a chip body, a chip pad on a surface of the chip body and a passivation layer on the chip body and on the chip pad, an encapsulation layer on side surfaces of the semiconductor chip within the through hole, and a guard ring on the passivation layer and on an edge portion of the chip body.

公开(公告)号：US20200161203A1

公开(公告)日：2020-05-21

申请号：US16679484

申请日：2019-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonsung Kim ,  Doohwan Lee

IPC: H01L23/31 ,  H01L23/13 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package may include: a frame having a cavity and including a wiring structure connecting first and second surfaces of the frame to each other; a first connection structure d on the second surface of the frame and including a first redistribution layer connected to the wiring structure; a semiconductor chip on the first connection structure within the cavity and having connection pads connected to the first redistribution layer; an encapsulant encapsulating the semiconductor chip, covering the first surface of the frame, and having an upper surface substantially coplanar with an upper surface of the wiring structure; and a second connection structure including an insulating layer disposed on the upper surfaces of the encapsulant and the wiring structure, a second redistribution layer on the insulating layer, and vias penetrating through the insulating layer and connecting the wiring structure and the second redistribution layer.

公开(公告)号：US12283577B2

公开(公告)日：2025-04-22

申请号：US17862482

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonsung Kim ,  Seokwon Lee

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/13 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L49/02

Abstract: A fan-out semiconductor package includes: a package body including a fan-in area corresponding to a through-hole located therein, a fan-out area surrounding the fan-in area, and a body interconnect structure arranged in the package body corresponding to the fan-out area; a fan-in chip structure located in the through-hole, the fan-in chip structure comprising a first chip, a capacitor chip arranged to be apart from the first chip, and a second chip disposed on both the first chip and the capacitor chip; a redistribution structure arranged on a bottom surface of the package body and a bottom surface of the fan-in chip structure and including a redistribution element extending to the fan-out area; and an interconnect via arranged on a top surface of the package body and electrically connected to the redistribution element in the fan-out area.

公开(公告)号：US20240040806A1

公开(公告)日：2024-02-01

申请号：US18125928

申请日：2023-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonsung Kim ,  Jihwang Kim ,  Jeongho Lee ,  Dongwook Kim ,  Wonkyoung Choi ,  Yunseok Choi

IPC: H10B80/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/36

CPC classification number: H10B80/00 ,  H01L23/5383 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/16 ,  H01L23/36 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253

Abstract: A semiconductor package includes a lower package, an upper package on the lower package, and an inter-package connector between the lower package and the upper package. The lower package includes a first redistribution structure, a first semiconductor chip mounted on a first mounting region of the first redistribution structure, a second semiconductor chip mounted on a second mounting region of the first redistribution structure, a molding layer on the first redistribution structure and in contact with a side wall of the first semiconductor chip and a side wall of the second semiconductor chip, and a conductive post passing through the molding layer and electrically connected to the first semiconductor chip through a first redistribution pattern of the first redistribution structure. The upper package is on the molding layer, vertically overlaps with the second mounting region of the first redistribution structure, and does not cover the first semiconductor chip.