公开(公告)号：US20240260266A1

公开(公告)日：2024-08-01

申请号：US18356896

申请日：2023-07-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro HOSODA ,  Masanori TSUTSUMI ,  Shunsuke TAKUMA ,  Seiji SHIMABUKURO ,  Tatsuya HINOUE ,  Takashi KASHIMURA ,  Tomohiro KUBO ,  Hisakazu OTOI ,  Hiroyuki TANAKA ,  Takumi MORIYAMA ,  Ryota SUZUKI

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/35

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, such that a first electrically conductive layer of the electrically conductive layers is in contact with an underlying silicon oxycarbide liner and with an overlying silicon oxycarbide liner, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory film containing a continuous memory material layer which continuously extends through the entire alternating stack.

公开(公告)号：US20240179908A1

公开(公告)日：2024-05-30

申请号：US18353621

申请日：2023-07-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro HOSODA ,  Kazuki ISOZUMI ,  Masanori TSUTSUMI

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, a source layer overlying the first-tier alternating stack, a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the source layer, a memory opening vertically extending through the first-tier alternating stack, the source layer, and the second-tier alternating stack, and a memory opening fill structure located in the memory opening. The memory opening fill structure includes a vertical semiconductor channel that extends through the first-tier alternating stack, the source layer, and the second-tier alternating stack. The vertical semiconductor channel has sidewall in contact with the source layer.

公开(公告)号：US20220181283A1

公开(公告)日：2022-06-09

申请号：US17113293

申请日：2020-12-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro HOSODA ,  Masanori TSUTSUMI ,  Sayako NAGAMINE

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11582

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers located between a drain-side dielectric layer and a source-side dielectric layer. Memory openings vertically extend through the alternating stack. Each of the memory openings has a greater lateral dimension an interface with the source-side dielectric layer than at an interface with the drain-side dielectric layer. Memory opening fill structures are located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel, a vertical stack of memory elements, and a drain region. A logic die may be bonded to a source-side dielectric layer side of the memory die.

公开(公告)号：US20210159167A1

公开(公告)日：2021-05-27

申请号：US16695775

申请日：2019-11-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori TSUTSUMI ,  Naohiro HOSODA ,  Shuichi HAMAGUCHI ,  Kazuki ISOZUMI ,  Genta MIZUNO ,  Yusuke MUKAE ,  Ryo NAKAMURA ,  Yu Yu UEDA

IPC: H01L23/522 ,  H01L23/532 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.

公开(公告)号：US20210005627A1

公开(公告)日：2021-01-07

申请号：US16503884

申请日：2019-07-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tatsuya HINOUE ,  Kengo KAJIWARA ,  Ryosuke ITOU ,  Naohiro HOSODA ,  Yohei MASAMORI ,  Kota FUNAYAMA ,  Keisuke TSUKAMOTO ,  Hirofumi WATATANI

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524

Abstract: First memory openings are formed through a first alternating stack of first insulating layers and first spacer material layers. Each first memory opening is filled with a first memory film, a sacrificial dielectric liner, and a first-tier opening fill material portion. Second memory openings are formed through a second alternating stack of second insulating layers and second spacer material layers. A second memory film is formed in each second memory opening. The first-tier opening fill material portions are removed selective to the sacrificial dielectric liners. The sacrificial dielectric liners are removed selective to the second memory films and the first memory films. A vertical semiconductor channel can be formed on each vertical stack of a first memory film and a second memory film.

公开(公告)号：US20180130812A1

公开(公告)日：2018-05-10

申请号：US15347101

申请日：2016-11-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro HOSODA ,  Takeshi KAWAMURA ,  Yoko FURIHATA ,  Kota FUNAYAMA

IPC: H01L27/115

CPC classification number: H01L27/11556 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support openings and first memory openings are formed through the first tier structure. A dielectric material portion providing electrical isolation from the substrate is formed in each first memory openings. A second tier structure including a second alternating stack of second insulating layers and second sacrificial material layers is formed the first tier structure. Second support openings and second memory openings are formed through the second tier structure above the first support openings and the first memory openings. Memory stack structures are formed in inter-tier openings formed by adjoining the first and second memory openings. The dielectric material portions provide electrical isolation between the substrate and the vertical semiconductor layers formed within support pillar structures to prevent or reduce electrical shorts to the substrate through the support pillar structures.