公开(公告)号：US20180331117A1

公开(公告)日：2018-11-15

申请号：US15593820

申请日：2017-05-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Monica TITUS ,  Zhixin CUI ,  Senaka KANAKAMEDALA ,  Yao-Sheng LEE ,  Chih-Yu LEE

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: A joint level dielectric material layer is formed over a first alternating stack of first insulating layers and first spacer material layers. A first memory opening is formed with a tapered sidewall of the joint level dielectric material layer. A second alternating stack of second insulating layers and second spacer material layers is formed over the joint level dielectric material layer. An inter-tier memory opening is formed, which includes a volume of an second memory opening that extends through the second alternating stack and a volume of the first memory opening. A memory film and a semiconductor channel are formed in the inter-tier memory opening with respective tapered portions overlying the tapered sidewall of the joint level dielectric material layer.

公开(公告)号：US20220285388A1

公开(公告)日：2022-09-08

申请号：US17192668

申请日：2021-03-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin CUI ,  Tatsuya HINOUE

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory material layer. A vertical stack of insulating material portions can be provided at levels of the insulating layers to provide a laterally-undulating profile to the memory material layer. Alternatively, a combination of inner insulating spacers and outer insulating spacers can be employed to provide a laterally-undulating profile to the memory material layer.

公开(公告)号：US20210366808A1

公开(公告)日：2021-11-25

申请号：US16921146

申请日：2020-07-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin CUI ,  Hirofumi TOKITA

IPC: H01L23/48 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A first-tier structure includes a first vertically alternating sequence of first continuous insulating layers and first continuous sacrificial material layers and a first-tier retro-stepped dielectric material portion overlying first stepped surfaces of the first vertically alternating sequence. A second vertically alternating sequence of second continuous insulating layers and second continuous sacrificial material layers is formed over the first-tier structure. Retro-stepped dielectric material portions are formed in each of the first-tier structure and the second-tier structure. After formation of memory stack structures, electrically conductive layers replace portions of the first and second continuous sacrificial material layers. Laterally-isolated contact via structures can be formed through the second-tier structure and a first-tier retro-stepped dielectric material portion on first electrically conductive layers in the first-tier structure. Sacrificial landing pad structures can be employed to enable concurrent formation of contact via cavities through the retro-stepped dielectric material portions.

公开(公告)号：US20210305384A1

公开(公告)日：2021-09-30

申请号：US16828129

申请日：2020-03-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin CUI ,  Hardwell CHIBVONGODZE ,  Masatoshi NISHIKAWA

IPC: H01L29/423 ,  H01L27/11582 ,  H01L29/417 ,  H01L21/28 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: A three-dimensional memory device includes an alternating stack of word-line-isolation insulating layers and word-line-level electrically conductive layers located over a substrate, a plurality of drain-select-level electrodes that are laterally spaced apart from each other overlying the alternating stack, memory stack structures containing a respective vertical semiconductor channel laterally surrounded by a respective memory film and vertically extending through the alternating stack and the plurality of drain-select-level electrodes, inter-select-gate electrodes located between a respective neighboring pair of the drain-select-level electrodes, and inter-select-gate dielectrics located between each of the inter-select-gate electrodes and a neighboring one of the drain-select-level electrodes. The inter-select-gate electrodes are not electrically connected to the drain-select-level electrodes.

公开(公告)号：US20200303397A1

公开(公告)日：2020-09-24

申请号：US16361722

申请日：2019-03-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin CUI ,  Kiyohiko SAKAKIBARA ,  Yanli ZHANG

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/28 ,  H01L21/311 ,  H01L29/423

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, drain-select-level trenches that vertically extend through at least one drain-select-level electrically conductive layer and laterally extend along a first horizontal direction and divide each drain-select-level electrically conductive layer into multiple drain-select-level electrically conductive strips, and pairs of vertical conductive strips located within a respective one of the drain-select-level trenches. Each of the vertical conductive strips has a pair of vertical straight sidewalls that laterally extends along the first horizontal direction. Each drain-select-level electrode may have at least one drain-select-level electrically conductive layer and at least one vertical conductive strip.

公开(公告)号：US20200286917A1

公开(公告)日：2020-09-10

申请号：US16881353

申请日：2020-05-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michimoto KAMINAGA ,  Zhixin CUI

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11565 ,  H01L21/768 ,  H01L27/11556 ,  H01L23/532 ,  H01L23/522 ,  H01L27/11575

Abstract: A contact via structure vertically extending through an alternating stack of insulating layers and electrically conductive layers is provided in a staircase region having stepped surfaces. The contact via structure is electrically isolated from each electrically conductive layer of the alternating stack except for an electrically conductive layer that directly underlies a horizontal interface of the stepped surfaces. A laterally-insulated structure includes a conductive via structure having an upper conductive via portion overlying and contacting an annular area of a top surface of one of the electrically conductive layers, a lower conductive via portion having a lesser lateral dimension than the upper conductive via portion and extending through at least a bottommost one of the electrically conductive layers, and an interconnection conductive via portion located between the upper conductive via portion and the lower conductive via portion and contacting a cylindrical sidewall of the one of the electrically conductive layers.

公开(公告)号：US20200251149A1

公开(公告)日：2020-08-06

申请号：US16269301

申请日：2019-02-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli ZHANG ,  Zhixin CUI ,  Akio NISHIDA ,  Johann ALSMEIER ,  Yan LI ,  Steven SPROUSE

IPC: G11C5/06 ,  G06F11/08 ,  G11C8/14 ,  H01L25/065 ,  H01L27/105 ,  H01L23/498 ,  H01L23/538

Abstract: A bonded assembly includes a memory die bonded to a support die. The memory die contains at least one three-dimensional array of memory elements, memory-die dielectric material layers, and memory-die bonding pads. The support die contains at least one peripheral circuitry including complementary metal-oxide-semiconductor (CMOS) devices and configured to generate control signals for, and receive sense signals from, the at least one three-dimensional array of memory elements and a functional module and configured to provide a functionality that is independent of operation of the at least one three-dimensional array of memory elements. The functional module may include an error correction code (ECC) module, a memory module configured to interface with an external processor module located outside of the memory die, a microprocessor unit module, a wireless communication module, and/or a system level controller module.

公开(公告)号：US20200185405A1

公开(公告)日：2020-06-11

申请号：US16215912

申请日：2018-12-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin CUI ,  Masatoshi NISHIKAWA ,  Ken OOWADA

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L23/528 ,  H01L21/311 ,  H01L21/762 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/28

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. The alternating stack includes a first region in which all layers of the alternating stack are present and a second region in which at least a topmost one of the electrically conductive layers is absent. First memory opening fill structures extend through the first region of the alternating stack, and second memory opening fill structures extend through the second region of the alternating stack. The first memory opening fill structures have a greater height than the second memory opening fill structures. Pocket doping regions extending over a respective subset of topmost electrically conductive layers for the memory opening fill structures can be formed to provide higher threshold voltages and to enable selective activation of vertical semiconductor channels connected a same bit line.