公开(公告)号：US20160284814A1

公开(公告)日：2016-09-29

申请号：US15176603

申请日：2016-06-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA ,  Ali SALIH

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/304 ,  H01L21/762 ,  H01L21/306

CPC classification number: H01L29/66333 ,  H01L21/265 ,  H01L21/3043 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/76224 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/7397

Abstract: In one embodiment, an IGBT is formed to include a plurality of termination trenches in a termination region of the IGBT. An embodiment may include that one end of one or more termination trenches may be exposed on one surface of the semiconductor device.

Abstract translation: 在一个实施例中，IGBT形成为在IGBT的端接区域中包括多个端接沟槽。 一个实施例可以包括一个或多个终止沟槽的一端可以暴露在半导体器件的一个表面上。

公开(公告)号：US20210313453A1

公开(公告)日：2021-10-07

申请号：US16841167

申请日：2020-04-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Mohammed T. QUDDUS ,  Mihir MUDHOLKAR ,  Ali SALIH

IPC: H01L29/66 ,  H01L29/872 ,  H01L29/423 ,  H01L29/812 ,  H01L21/762

Abstract: A semiconductor device structure comprises a region of semiconductor material comprising a first conductivity type, a first major surface, and a second major surface opposite to the first major surface. A first trench gate structure includes a first trench extending from the first major surface into the region of semiconductor material, a first dielectric structure is over sidewall surfaces and a portion of a lower surface of the first trench, wherein the first dielectric structure comprises a first opening adjacent to the lower surface of the first trench, a first recessed contact extends through the first opening, and a first contact region is over the first recessed contact within the first trench, wherein the first recessed contact and the first contact region comprise different materials. A first doped region comprising a second dopant conductivity type opposite to the first conductivity type is in the region of semiconductor material and is spaced apart from the first major surface and below the first trench. A gate contact region is in the region of semiconductor material and is electrically connected to the first doped region.

公开(公告)号：US20200161142A1

公开(公告)日：2020-05-21

申请号：US16388361

申请日：2019-04-18

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Ali SALIH

IPC: H01L21/324 ,  H01L21/322 ,  H01L21/02 ,  H01L29/20 ,  H01L29/786 ,  H01L29/66

Abstract: Systems and methods of the disclosed embodiments include reducing defects in a semiconductor layer. The defects may be reduced by forming the semiconductor layer on a substrate, removing at least a portion the substrate from an underside of the semiconductor layer, and annealing the semiconductor layer to reduce the defects in the layer. The annealing includes focusing energy at the layer.

公开(公告)号：US20190245072A1

公开(公告)日：2019-08-08

申请号：US16387874

申请日：2019-04-18

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul JEON ,  Chun-Li LIU ,  Ali SALIH

IPC: H01L29/778 ,  H01L23/58 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L23/495 ,  H01L29/40 ,  H01L29/20 ,  H01L29/417 ,  H01L29/16

CPC classification number: H01L29/778 ,  H01L23/4952 ,  H01L23/49537 ,  H01L23/585 ,  H01L27/0883 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1066 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/42316

Abstract: Implementations of semiconductor devices may include: a plurality of drain fingers and a plurality of source fingers interdigitated with one another; at least one gate; and at gate bus formed to completely surround the plurality of drain fingers and the plurality of source fingers; wherein the gate bus is mechanically and electrically coupled to the at least one gate.

公开(公告)号：US20180240900A1

公开(公告)日：2018-08-23

申请号：US15955555

申请日：2018-04-17

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul JEON ,  Chun-Li LIU ,  Ali SALIH

IPC: H01L29/778 ,  H01L23/495 ,  H01L29/20 ,  H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L27/088 ,  H01L29/16

CPC classification number: H01L29/778 ,  H01L23/4952 ,  H01L23/49537 ,  H01L23/585 ,  H01L27/0883 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1066 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/42316

Abstract: Implementations of semiconductor devices may include: a plurality of drain fingers and a plurality of source fingers interdigitated with one another; at least one gate; and at gate bus formed to completely surround the plurality of drain fingers and the plurality of source fingers; wherein the gate bus is mechanically and electrically coupled to the at least one gate.

公开(公告)号：US20180138306A1

公开(公告)日：2018-05-17

申请号：US15807237

申请日：2017-11-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul JEON ,  Ali SALIH ,  Llewellyn Vaughan-Edmunds

IPC: H01L29/778 ,  H01L29/417 ,  H01L29/08

Abstract: High-electron-mobility transistor (HEMT) devices are described in this patent application. In some implementations, the HEMT devices can include a back barrier hole injection structure. In some implementations, the HEMT devices include a conductive striped portion electrically coupled to a drain contact.

公开(公告)号：US20180019332A1

公开(公告)日：2018-01-18

申请号：US15208466

申请日：2016-07-12

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul JEON ,  Chun-Li LIU ,  Ali SALIH

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/16 ,  H01L23/495 ,  H01L29/06 ,  H01L27/088 ,  H01L29/417 ,  H01L29/20

CPC classification number: H01L29/778 ,  H01L23/4952 ,  H01L23/49537 ,  H01L23/585 ,  H01L27/0883 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1066 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/42316

Abstract: Implementations of semiconductor devices may include: a plurality of drain fingers and a plurality of source fingers interdigitated with one another; at least one gate; and at gate bus formed to completely surround the plurality of drain fingers and the plurality of source fingers; wherein the gate bus is mechanically and electrically coupled to the at least one gate.

公开(公告)号：US20150108569A1

公开(公告)日：2015-04-23

申请号：US14297204

申请日：2014-06-05

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA ,  Zia HOSSAIN ,  Ali SALIH

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/76205 ,  H01L21/76816 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: In an embodiment, a method of forming a semiconductor may include forming a plurality of active trenches and forming a termination trench substantially surrounding an outer periphery of the plurality of active trenches. The method may also include forming at least one active trench of the plurality of active trenches having corners linking trench ends to sides of active trenches wherein each active trench of the plurality of active trenches has a first profile along the first length and a second profile at or near the trench ends; and forming a termination trench substantially surrounding an outer periphery of the plurality of active trenches and having a second profile wherein one of the first profile or the second profile includes a non-linear shape.

Abstract translation: 在一个实施例中，形成半导体的方法可以包括形成多个有源沟槽并且形成基本上围绕多个有源沟槽的外周边的端接沟槽。 该方法还可以包括形成多个有源沟槽中的至少一个有源沟槽，其具有将沟槽端部连接到有源沟槽侧面的拐角，其中多个有源沟槽中的每个有源沟槽具有沿第一长度的第一分布， 或在沟槽末端附近; 以及形成基本上围绕所述多个有源沟槽的外周边的终端沟槽，并且具有第二形状，其中所述第一形状或所述第二形状中的一个包括非线性形状。

公开(公告)号：US20190267252A1

公开(公告)日：2019-08-29

申请号：US16406899

申请日：2019-05-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chun-Li LIU ,  Ali SALIH ,  Mingjiao LIU

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/492 ,  H01L21/52 ,  H01L23/498 ,  H01L29/20

Abstract: In accordance with an embodiment, a semiconductor component includes a support having a side in which a device receiving structure and an interconnect structure are formed and a side from which a plurality of leads extends. A semiconductor device having a control terminal and first and second current carrying terminals and configured from a III-N semiconductor material is mounted to the device receiving structure. A first electrical interconnect is coupled between the first current carrying terminal of the semiconductor device and a first lead. A second electrical interconnect is coupled between the control terminal of the semiconductor device and a second lead.

公开(公告)号：US20190123041A1

公开(公告)日：2019-04-25

申请号：US16215870

申请日：2018-12-11

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Balaji PADMANABHAN ,  Prasad VENKATRAMAN ,  Zia HOSSAIN ,  Chun-Li LIU ,  Jason MCDONALD ,  Ali SALIH ,  Alexander YOUNG

IPC: H01L27/06 ,  H01L29/10 ,  H01L27/02 ,  H01L23/367 ,  H01L29/417 ,  H01L29/778 ,  H01L21/74 ,  H01L21/8258

CPC classification number: H01L27/0629 ,  H01L21/743 ,  H01L21/8258 ,  H01L23/3677 ,  H01L23/481 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/0688 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/7783 ,  H01L29/861 ,  H01L29/872 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A cascode switch structure includes a group III-V transistor structure having a first current carrying electrode, a second current carrying electrode and a first control electrode. A semiconductor MOSFET device includes a third current carrying electrode electrically connected to the first current carrying electrode, a fourth current carrying electrode electrically connected to the first control electrode, and a second control electrode. A first diode includes a first cathode electrode electrically connected to the second current carrying electrode and a first anode electrode. A second diode includes a second anode electrode electrically connected to the first anode electrode and a second cathode electrode electrically connected to the fourth current carrying electrode. In one embodiment, the group III-V transistor structure, the first diode, and the second diode are integrated within a common substrate.