公开(公告)号：US20170040447A1

公开(公告)日：2017-02-09

申请号：US15333441

申请日：2016-10-25

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Shengling DENG ,  Zia HOSSAIN

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7397

Abstract: A semiconductor device includes a semiconductor region with a charge balance region on a junction blocking region, the junction blocking region having a lower doping concentration. The junction blocking region extends between a pair of trench structures in cross-sectional view. The trench structures are provided in the semiconductor region and include at least one insulated electrode. In some embodiments, the semiconductor device further includes a first doped region disposed between the pair of trench structures. The semiconductor device may further include one or more features configured to improve operating performance The features include a localized doped region adjoining a lower surface of a first doped region and spaced apart from the trench structure, a notch disposed proximate to the lower surface of the first doped region, and/or the at least one insulated electrode configured to have a wide portion adjoining a narrow portion.

Abstract translation: 半导体器件包括在结阻挡区上具有电荷平衡区的半导体区，该结阻挡区具有较低的掺杂浓度。 结阻挡区域在横截面图中在一对沟槽结构之间延伸。 沟槽结构设置在半导体区域中，并且包括至少一个绝缘电极。 在一些实施例中，半导体器件还包括设置在该对沟槽结构之间的第一掺杂区域。 半导体器件还可以包括被配置为改善操作性能的一个或多个特征。特征包括邻接第一掺杂区域的下表面并与沟槽结构间隔开的局部掺杂区域，靠近第一掺杂区域的下表面设置的凹口 掺杂区域和/或所述至少一个绝缘电极，其被配置为具有邻近窄部分的宽部分。

公开(公告)号：US20160172234A1

公开(公告)日：2016-06-16

申请号：US15047874

申请日：2016-02-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA ,  Zia HOSSAIN ,  Ali SALIH

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/768

CPC classification number: H01L21/76205 ,  H01L21/76816 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: In an embodiment, a method of forming a semiconductor may include forming a plurality of active trenches and forming a termination trench substantially surrounding an outer periphery of the plurality of active trenches. The method may also include forming at least one active trench of the plurality of active trenches having corners linking trench ends to sides of active trenches wherein each active trench of the plurality of active trenches has a first profile along the first length and a second profile at or near the trench ends; and forming a termination trench substantially surrounding an outer periphery of the plurality of active trenches and having a second profile wherein one of the first profile or the second profile includes a non-linear shape.

公开(公告)号：US20160020288A1

公开(公告)日：2016-01-21

申请号：US14336770

申请日：2014-07-21

Applicant: Semiconductor Components Industries, LLC

Inventor： Shengling DENG ,  Zia HOSSAIN

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7397

Abstract: A semiconductor device includes a semiconductor region with a charge balance region on a junction blocking region, which has a lower doping concentration. A trench structure having an insulated shield electrode and an insulated gate electrode is provided in the semiconductor region. The semiconductor device further includes one or more features configured to improve operating performance. The features include terminating the trench structure in the junction blocking region, providing a localized doped region adjoining a lower surface of a body region and spaced apart from the trench structure, disposing a notch proximate to the lower surface of the body region, and/or configuring the insulated shield electrode to have a wide portion adjoining a narrow portion.

Abstract translation: 半导体器件包括在结阻挡区域具有电荷平衡区域的半导体区域，其具有较低的掺杂浓度。 在半导体区域中设置有具有绝缘屏蔽电极和绝缘栅电极的沟槽结构。 半导体器件还包括配置成改善操作性能的一个或多个特征。 这些特征包括终止接合阻挡区域中的沟槽结构，提供邻接主体区域的下表面并与沟槽结构间隔开的局部掺杂区域，在靠近体区域的下表面设置切口，和/或 将绝缘屏蔽电极配置成具有邻近窄部分的宽部分。

公开(公告)号：US20240413196A1

公开(公告)日：2024-12-12

申请号：US18701585

申请日：2023-09-11

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Sauvik CHOWDHURY ,  Zia HOSSAIN ,  Joseph Andrew YEDINAK

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/49

Abstract: Shielded gate semiconductor devices are disclosed for use in high power applications such as electric vehicles and industrial applications. The devices are formed as mesa (106)/trench (400) structures in which shielded gate electrodes are formed in the trenches. Various trench structures (400, 500, 600, 700) are presented that include tapered portions (401) and end tabs (502, 602, 702, 802) that can be beneficial in managing the distribution of electric charge and associated electric fields. The tapered trenches (400) can be used to increase and stabilize breakdown voltages in a termination region (104) of a semiconductor die (100).

公开(公告)号：US20200295149A1

公开(公告)日：2020-09-17

申请号：US16450149

申请日：2019-06-24

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Balaji PADMANABHAN ,  Prasad VENKATRAMAN ,  Zia HOSSAIN ,  Donald ZAREMBA ,  Gordon M. GRIVNA ,  Alexander YOUNG

IPC: H01L29/423 ,  H01L21/762

Abstract: Systems and methods of the disclosed embodiments include an electronic device that has a gate electrode for supplying a gate voltage, a source, a drain, and a channel doped to enable a current to flow from the drain to the source when a voltage is applied to the gate electrode. The electronic device may also include a gate insulator between the channel and the gate electrode. The gate insulator may include a first gate insulator section comprising a first thickness, and a second gate insulator section comprising a second thickness that is less than the first thickness. The gate insulator sections thereby improve the safe operating area by enabling the current to flow through the second gate insulator section at a lower voltage than the first gate insulator section.

公开(公告)号：US20190123043A1

公开(公告)日：2019-04-25

申请号：US16225930

申请日：2018-12-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Balaji PADMANABHAN ,  Prasad VENKATRAMAN ,  Zia HOSSAIN ,  Chun-Li LIU ,  Woochul JEON ,  Jason MCDONALD

IPC: H01L27/06 ,  H01L29/10 ,  H01L27/02 ,  H01L23/367 ,  H01L29/417 ,  H01L29/778 ,  H01L21/74 ,  H01L21/8258

Abstract: A method for forming a cascode rectifier structure includes providing a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are provided adjacent a major surface of the heterostructure and a control electrode is provided between the first and second current carrying electrode. A rectifier device is provided integrated with the group III-V semiconductor structure and is electrically connected to the first current carrying electrode and to a third electrode. The control electrode is provided further electrically connected to the semiconductor substrate and the second current path is generally perpendicular to a primary current path between the first and second current carrying electrodes. The cascode rectifier structure is provided as a two terminal device.

公开(公告)号：US20190067266A1

公开(公告)日：2019-02-28

申请号：US16104039

申请日：2018-08-16

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Balaji PADMANABHAN ,  Kirk K. HUANG ,  Prasad VENKATRAMAN ,  Emily M. LINEHAN ,  Zia HOSSAIN

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L27/088

Abstract: An electronic device can include a transistor having a gate electrode, a first portion, and a second portion, wherein along the gate electrode, the first portion of the transistor has a first gate-to-drain capacitance and a first gate-to-source capacitance, the second portion of the transistor has a second gate-to-drain capacitance and a second gate-to-source capacitance, and a ratio of the first gate-to-drain capacitance to the first gate-to-source capacitance is less than a ratio of the second gate-to-drain capacitance to the second gate-to-source capacitance.

公开(公告)号：US20160126348A1

公开(公告)日：2016-05-05

申请号：US14992106

申请日：2016-01-11

Applicant: Semiconductor Components Industries, LLC

Inventor： Shengling DENG ,  Zia HOSSAIN

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7397

Abstract: A semiconductor device includes a semiconductor region with a charge balance region on a junction blocking region, which has a lower doping concentration. A trench structure having an insulated shield electrode and an insulated gate electrode is provided in the semiconductor region. The semiconductor device further includes one or more features configured to improve operating performance. The features include terminating the trench structure in the junction blocking region, providing a localized doped region adjoining a lower surface of a body region and spaced apart from the trench structure, disposing a notch proximate to the lower surface of the body region, and/or configuring the insulated shield electrode to have a wide portion adjoining a narrow portion.

Abstract translation: 半导体器件包括在结阻挡区域具有电荷平衡区域的半导体区域，其具有较低的掺杂浓度。 在半导体区域中设置有具有绝缘屏蔽电极和绝缘栅电极的沟槽结构。 半导体器件还包括配置成改善操作性能的一个或多个特征。 这些特征包括终止接合阻挡区域中的沟槽结构，提供邻接主体区域的下表面并与沟槽结构间隔开的局部掺杂区域，在靠近体区域的下表面设置切口，和/或 将绝缘屏蔽电极配置成具有邻近窄部分的宽部分。

公开(公告)号：US20150295029A1

公开(公告)日：2015-10-15

申请号：US14249882

申请日：2014-04-10

Applicant: Semiconductor Components Industries, LLC

Inventor： Jaume ROIG GUITART ,  Zia HOSSAIN ,  Peter MOENS ,  Gordon M. GRIVNA

IPC: H01L29/06 ,  H01L29/423 ,  H01L21/762 ,  H01L29/40

CPC classification number: H01L29/0649 ,  H01L21/76229 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: An electronic device can include an electronic component and a termination region adjacent to the electronic component region. In an embodiment, the termination region can include an insulating region that extends a depth into a semiconductor layer, wherein the depth is less than 50% of the thickness of the semiconductor layer. In another embodiment, the termination region can include a first insulating region that extends a first depth into the semiconductor layer, and a second insulating region that extends a second depth into the semiconductor layer, wherein the second depth is less than the first depth. In another aspect, a process of forming an electronic device can include patterning a semiconductor layer to define a trench within termination region while another trench is being formed for an electronic component within an electronic component region.

Abstract translation: 电子设备可以包括电子部件和与电子部件区域相邻的端接区域。 在一个实施例中，终端区域可以包括将深度延伸到半导体层中的绝缘区域，其中深度小于半导体层厚度的50％。 在另一个实施例中，终端区域可以包括将第一深度延伸到半导体层中的第一绝缘区域和将第二深度延伸到半导体层中的第二绝缘区域，其中第二深度小于第一深度。 在另一方面，形成电子器件的工艺可以包括图案化半导体层以限定终止区域内的沟槽，同时为电子部件区域内的电子部件形成另一个沟槽。

公开(公告)号：US20240014261A1

公开(公告)日：2024-01-11

申请号：US18469780

申请日：2023-09-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Shengling DENG ,  Dean E. PROBST ,  Zia HOSSAIN

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/739 ,  H01L29/868 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/0653 ,  H01L29/7804 ,  H01L29/7397 ,  H01L29/868 ,  H01L29/6634 ,  H01L29/0882 ,  H01L29/7813 ,  H01L29/66712 ,  H01L29/66348 ,  H01L29/1095

Abstract: In a general aspect, a method can include forming well region of one conductivity type in a semiconductor region of another conductivity type An interface between the well region and the semiconductor region can define a diode junction at a depth below an upper surface of the semiconductor region. The method can further include forming at least one dielectric region in the semiconductor region. A dielectric region of the at least one dielectric region can have an upper surface that is disposed in the well region at a depth in the semiconductor region that is above the depth of the diode junction; and a lower surface that is disposed in the semiconductor region at a depth in the semiconductor region that is the same depth as the diode junction or below the depth of the diode junction.