公开(公告)号：US09806096B2

公开(公告)日：2017-10-31

申请号：US14944444

申请日：2015-11-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masahiko Hayakawa ,  Mitsunori Sakama ,  Satoshi Toriumi

IPC: H01L29/80 ,  H01L21/31 ,  H01L27/12 ,  H01L21/314 ,  H01L21/762 ,  H01L29/786 ,  G02F1/1368 ,  H01L27/32 ,  H01L21/20

CPC classification number: H01L21/02686 ,  G02F1/1368 ,  H01L21/2026 ,  H01L21/3145 ,  H01L21/7624 ,  H01L27/12 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1237 ,  H01L27/1248 ,  H01L27/3248 ,  H01L27/3258 ,  H01L29/78603 ,  H01L29/78621

Abstract: An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si.

公开(公告)号：US09722056B2

公开(公告)日：2017-08-01

申请号：US15276993

申请日：2016-09-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Akihisa Shimomura ,  Yasumasa Yamane ,  Yuhei Sato ,  Tetsuhiro Tanaka ,  Masashi Tsubuku ,  Toshihiko Takeuchi ,  Ryo Tokumaru ,  Mitsuhiro Ichijo ,  Satoshi Toriumi ,  Takashi Ohtsuki ,  Toshiya Endo

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: A change in electrical characteristics is suppressed and reliability in a semiconductor device using a transistor including an oxide semiconductor is improved. Oxygen is introduced into a surface of an insulating film, and then, an oxide semiconductor, a layer which is capable of blocking oxygen, a gate insulating film, and other films which composes a transistor are formed. For at least one of the first gate insulating film and the insulating film, three signals in Electron Spin Resonance Measurement are each observed in a certain range of g-factor. Reducing the sum of the spin densities of the signals will improve reliability of the semiconductor device.

公开(公告)号：US11217703B2

公开(公告)日：2022-01-04

申请号：US16905120

申请日：2020-06-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Satoshi Toriumi ,  Takashi Hamada ,  Tetsunori Maruyama ,  Yuki Imoto ,  Yuji Asano ,  Ryunosuke Honda ,  Shunpei Yamazaki

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/51 ,  H01L29/49 ,  H01L29/417 ,  H01L27/12 ,  H01L27/146 ,  H01L27/1156 ,  H01L27/06 ,  H01L29/423 ,  H01L21/822

Abstract: A minute transistor is provided that includes a first insulator, a second insulator, a first, conductor, a second conductor, and third conductor, in which an angle is formed between a side surface of the first insulator and a top surface of the first conductor, and a length between the first conductor and a surface of the second conductor closest to the first conductor is at least greater than a length between the first conductor and the third conductor.

公开(公告)号：US10693013B2

公开(公告)日：2020-06-23

申请号：US15091009

申请日：2016-04-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Satoshi Toriumi ,  Takashi Hamada ,  Tetsunori Maruyama ,  Yuki Imoto ,  Yuji Asano ,  Ryunosuke Honda ,  Shunpei Yamazaki

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/51 ,  H01L29/49 ,  H01L29/417 ,  H01L27/12 ,  H01L27/146 ,  H01L27/1156 ,  H01L27/06 ,  H01L29/423 ,  H01L21/822

Abstract: A minute transistor with low parasitic capacitance, high frequency characteristics, favorable electrical characteristics, stable electrical characteristics, and low off-state current is provided. A semiconductor device includes a semiconductor over a substrate, a source and a drain over the semiconductor, a first insulator over the source and the drain, a second insulator over the semiconductor, a third insulator in contact with a side surface of the first insulator and over the second insulator, and a gate over the third insulator. The semiconductor includes a first region overlapping with the source, a second region overlapping with the drain, and a third region overlapping with the gate. The length between a top surface of the third region of the semiconductor and a bottom surface of the gate is longer than the length between the first region and the third region.

公开(公告)号：US09478664B2

公开(公告)日：2016-10-25

申请号：US14575052

申请日：2014-12-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Akihisa Shimomura ,  Yasumasa Yamane ,  Yuhei Sato ,  Tetsuhiro Tanaka ,  Masashi Tsubuku ,  Toshihiko Takeuchi ,  Ryo Tokumaru ,  Mitsuhiro Ichijo ,  Satoshi Toriumi ,  Takashi Ohtsuki ,  Toshiya Endo

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: A change in electrical characteristics is suppressed and reliability in a semiconductor device using a transistor including an oxide semiconductor is improved. The semiconductor device includes an oxide semiconductor film over an insulating surface, an antioxidant film over the insulating surface and the oxide semiconductor film, a pair of electrodes in contact with the antioxidant film, a gate insulating film over the pair of electrodes, and a gate electrode which is over the gate insulating film and overlaps with the oxide semiconductor film. In the antioxidant film, a width of a region overlapping with the pair of electrodes is longer than a width of a region not overlapping with the pair of electrodes.

Abstract translation: 抑制了电特性的变化，并且提高了使用包括氧化物半导体的晶体管的半导体器件的可靠性。 半导体器件包括绝缘表面上的氧化物半导体膜，绝缘表面上的抗氧化膜和氧化物半导体膜，与抗氧化膜接触的一对电极，一对电极上的栅极绝缘膜，以及栅极 电极，其在栅极绝缘膜上方并与氧化物半导体膜重叠。 在抗氧化剂膜中，与该对电极重叠的区域的宽度比不与该对电极重叠的区域的宽度长。

公开(公告)号：US09450132B2

公开(公告)日：2016-09-20

申请号：US14514552

申请日：2014-10-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Sho Kato ,  Yoshikazu Hiura ,  Akihisa Shimomura ,  Takashi Ohtsuki ,  Satoshi Toriumi ,  Yasuyuki Arai

IPC: H01L31/077 ,  H01L31/20 ,  H01L21/02 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/075 ,  H01L31/18

CPC classification number: H01L31/077 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/075 ,  H01L31/1804 ,  H01L31/20 ,  Y02E10/547 ,  Y02E10/548 ,  Y02P70/521

Abstract: An object is to increase conversion efficiency of a photoelectric conversion device without increase in the manufacturing steps. The photoelectric conversion device includes a first semiconductor layer formed using a single crystal semiconductor having one conductivity type which is formed over a supporting substrate, a buffer layer including a single crystal region and an amorphous region, a second semiconductor layer which includes a single crystal region and an amorphous region and is provided over the butler layer, and a third semiconductor layer having a conductivity type opposite to the one conductivity type, which is provided over the second semiconductor layer. A proportion of the single crystal region is higher than that of the amorphous region on the first semiconductor layer side in the second semiconductor layer, and the proportion of the amorphous region is higher than that of the single crystal region on the third semiconductor layer side.

Abstract translation: 目的在于提高光电转换装置的转换效率，而不增加制造步骤。 光电转换装置包括使用在支撑基板上形成的具有一种导电类型的单晶半导体形成的第一半导体层，包括单晶区域和非晶区域的缓冲层，包括单晶区域的第二半导体层 和非晶区域，并且设置在管状层上方，以及设置在第二半导体层上的具有与一种导电类型相反的导电类型的第三半导体层。 单晶区域的比例高于第二半导体层中的第一半导体层侧的非晶区域的比例，并且非晶区域的比例高于第三半导体层侧的单晶区域的比例。

公开(公告)号：US20160172382A1

公开(公告)日：2016-06-16

申请号：US14944444

申请日：2015-11-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masahiko Hayakawa ,  Mitsunori Sakama ,  Satoshi Toriumi

IPC: H01L27/12 ,  G02F1/1368 ,  H01L27/32

CPC classification number: H01L21/02686 ,  G02F1/1368 ,  H01L21/2026 ,  H01L21/3145 ,  H01L21/7624 ,  H01L27/12 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1237 ,  H01L27/1248 ,  H01L27/3248 ,  H01L27/3258 ,  H01L29/78603 ,  H01L29/78621

Abstract: An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si.

公开(公告)号：US09196632B2

公开(公告)日：2015-11-24

申请号：US14105575

申请日：2013-12-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masahiko Hayakawa ,  Mitsunori Sakama ,  Satoshi Toriumi

IPC: H01L29/80 ,  H01L21/31 ,  H01L27/12 ,  H01L21/314 ,  H01L21/762 ,  H01L29/786 ,  G02F1/1368 ,  H01L21/20

CPC classification number: H01L21/02686 ,  G02F1/1368 ,  H01L21/2026 ,  H01L21/3145 ,  H01L21/7624 ,  H01L27/12 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1237 ,  H01L27/1248 ,  H01L27/3248 ,  H01L27/3258 ,  H01L29/78603 ,  H01L29/78621

Abstract: An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si.

公开(公告)号：US20140139776A1

公开(公告)日：2014-05-22

申请号：US14105575

申请日：2013-12-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masahiko Hayakawa ,  Mitsunori Sakama ,  Satoshi Toriumi

IPC: H01L27/12 ,  G02F1/1368

CPC classification number: H01L21/02686 ,  G02F1/1368 ,  H01L21/2026 ,  H01L21/3145 ,  H01L21/7624 ,  H01L27/12 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1237 ,  H01L27/1248 ,  H01L27/3248 ,  H01L27/3258 ,  H01L29/78603 ,  H01L29/78621

Abstract: An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si.

Abstract translation: 本发明的目的是防止TFT（薄膜晶体管）的劣化。 通过在TFT的半导体层和衬底之间形成氧化硅氮化物膜，可以防止通过BT测试的TFT的劣化，其中氧化硅氮化物膜的浓度为N与 Si的浓度。