公开(公告)号：US20150060844A1

公开(公告)日：2015-03-05

申请号：US14462824

申请日：2014-08-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hidekazu Miyairi ,  Kazuya Hanaoka ,  Suguru Hondo ,  Shunpei Yamazaki

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/66969 ,  H01L29/7854 ,  H01L29/78621 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A semiconductor device that operates at high speed. A semiconductor device with favorable switching characteristics. A highly integrated semiconductor device. A miniaturized semiconductor device. The semiconductor device is formed by: forming a semiconductor film including an opening, on an insulating surface; forming a conductive film over the semiconductor film and in the opening, and removing the conductive film over the semiconductor film to form a conductive pillar in the opening; forming an island-shaped mask over the conductive pillar and the semiconductor film; etching the conductive pillar and the semiconductor film using the mask to form a first electrode and a first semiconductor; forming a gate insulating film on a top surface and a side surface of the first semiconductor; and forming a gate electrode that is in contact with a top surface of the gate insulating film and faces the top surface and the side surface of the first semiconductor.

Abstract translation: 一种高速运转的半导体器件。 具有良好开关特性的半导体器件。 高度集成的半导体器件。 小型半导体器件。 半导体器件通过以下方式形成：在绝缘表面上形成包括开口的半导体膜; 在所述半导体膜和所述开口中形成导电膜，并且在所述半导体膜上除去所述导电膜以在所述开口中形成导电柱; 在导电柱和半导体膜上形成岛状掩模; 使用掩模蚀刻导电柱和半导体膜以形成第一电极和第一半导体; 在第一半导体的顶表面和侧表面上形成栅极绝缘膜; 以及形成与所述栅极绝缘膜的顶表面接触并且面对所述第一半导体的顶表面和侧表面的栅电极。

公开(公告)号：US10096489B2

公开(公告)日：2018-10-09

申请号：US14635324

申请日：2015-03-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Suguru Hondo ,  Naoto Yamade

IPC: H01L21/425 ,  H01L21/465 ,  H01L29/786 ,  H01L29/66

Abstract: Provided is a method for manufacturing a semiconductor device with favorable electrical characteristics. The following steps are performed in the following order: forming an oxide semiconductor film over a substrate having a substantially planar surface; selectively etching the oxide semiconductor film to form an oxide semiconductor layer; implanting an oxygen ion on a top surface of the oxide semiconductor layer and a side surface of the oxide semiconductor layer in a cross-section perpendicular to the substantially planar surface in a channel width direction of the oxide semiconductor layer from an angle 0°

公开(公告)号：US09947794B2

公开(公告)日：2018-04-17

申请号：US15432961

申请日：2017-02-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu Miyairi ,  Kazuya Hanaoka ,  Suguru Hondo ,  Shunpei Yamazaki

IPC: H01L29/12 ,  H01L29/78 ,  H01L29/66 ,  H01L29/24 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/66969 ,  H01L29/7854 ,  H01L29/78621 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A semiconductor device that operates at high speed. A semiconductor device with favorable switching characteristics. A highly integrated semiconductor device. A miniaturized semiconductor device. The semiconductor device is formed by: fainting a semiconductor film including an opening, on an insulating surface; forming a conductive film over the semiconductor film and in the opening, and removing the conductive film over the semiconductor film to form a conductive pillar in the opening; forming an island-shaped mask over the conductive pillar and the semiconductor film; etching the conductive pillar and the semiconductor film using the mask to form a first electrode and a first semiconductor; forming a gate insulating film on a top surface and a side surface of the first semiconductor; and forming a gate electrode that is in contact with a top surface of the gate insulating film and faces the top surface and the side surface of the first semiconductor.

公开(公告)号：US09899533B2

公开(公告)日：2018-02-20

申请号：US14799015

申请日：2015-07-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Atsuo Isobe ,  Yuki Hata ,  Suguru Hondo

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L49/02 ,  H01L27/12 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L27/1255 ,  H01L28/60 ,  H01L29/0692 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/78696

Abstract: A transistor including an oxide semiconductor and having favorable operation characteristics is provided. Further, by using the transistor, a semiconductor having improved operation characteristics can be provided. In planar view, one of a source electrode and a drain electrode of the transistor is surrounded by a ring-shaped gate electrode. Further, in planar view, one of the source electrode and the drain electrode of the transistor is surrounded by a channel formation region. Accordingly, the source electrode is not electrically connected to the drain electrode through a parasitic channel generated in an end portion of an island-shaped oxide semiconductor layer.

公开(公告)号：US09837551B2

公开(公告)日：2017-12-05

申请号：US14258528

申请日：2014-04-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Suguru Hondo ,  Kazuya Hanaoka ,  Shinya Sasagawa ,  Naoto Kusumoto

IPC: H01L29/786 ,  H01L29/417

CPC classification number: H01L29/78696 ,  H01L29/41733 ,  H01L29/7869

Abstract: Provided is a semiconductor device that can be miniaturized in a simple process and that can prevent deterioration of electrical characteristics due to miniaturization. The semiconductor device includes an oxide semiconductor layer, a first conductor in contact with the oxide semiconductor layer, and an insulator in contact with the first conductor. Further, an opening portion is provided in the oxide semiconductor layer, the first conductor, and the insulator. In the opening portion, side surfaces of the oxide semiconductor layer, the first conductor, and the insulator are aligned, and the oxide semiconductor layer and the first conductor are electrically connected to a second conductor by side contact.

公开(公告)号：US09685500B2

公开(公告)日：2017-06-20

申请号：US14645566

申请日：2015-03-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yutaka Shionoiri ,  Tomoaki Atsumi ,  Shuhei Nagatsuka ,  Yutaka Okazaki ,  Suguru Hondo

IPC: H01L29/12 ,  H01L29/04 ,  H01L27/12 ,  H01L29/786 ,  H01L29/24 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/06

CPC classification number: H01L29/045 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device with a transistor having favorable electrical characteristics is provided. The semiconductor device has a memory circuit and a circuit that are over the same substrate. The memory circuit includes a capacitor, a first transistor, and a second transistor. A gate of the first transistor is electrically connected to the capacitor and one of a source and a drain of the second transistor. The circuit includes a third transistor and a fourth transistor that are electrically connected to each other in series. The first transistor and the third transistor each include an active layer including silicon, and the second transistor and the fourth transistor each include an active layer including an oxide semiconductor.

公开(公告)号：US09112037B2

公开(公告)日：2015-08-18

申请号：US13758291

申请日：2013-02-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Atsuo Isobe ,  Yuki Hata ,  Suguru Hondo

IPC: H01L29/04 ,  H01L29/786 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7869 ,  H01L27/1255 ,  H01L28/60 ,  H01L29/0692 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/78696

Abstract: A transistor including an oxide semiconductor and having favorable operation characteristics is provided. Further, by using the transistor, a semiconductor having improved operation characteristics can be provided. In planar view, one of a source electrode and a drain electrode of the transistor is surrounded by a ring-shaped gate electrode. Further, in planar view, one of the source electrode and the drain electrode of the transistor is surrounded by a channel formation region. Accordingly, the source electrode is not electrically connected to the drain electrode through a parasitic channel generated in an end portion of an island-shaped oxide semiconductor layer.

Abstract translation: 提供一种包含氧化物半导体并具有良好操作特性的晶体管。 此外，通过使用晶体管，可以提供具有改善的操作特性的半导体。 在平面图中，晶体管的源极和漏极中的一个被环形栅电极包围。 此外，在平面图中，晶体管的源电极和漏电极之一被沟道形成区域包围。 因此，源电极通过在岛状氧化物半导体层的端部中产生的寄生沟道而不与漏电极电连接。

公开(公告)号：US09048265B2

公开(公告)日：2015-06-02

申请号：US13897502

申请日：2013-05-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Suguru Hondo ,  Akihisa Shimomura ,  Masaki Koyama ,  Motomu Kurata ,  Kazuya Hanaoka ,  Sho Nagamatsu ,  Kosei Nei ,  Toru Hasegawa

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L21/46 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: A transistor including an oxide semiconductor film, which has stable electric characteristics is provided. A transistor including an oxide semiconductor film, which has excellent on-state characteristics is also provided. A semiconductor device in which an oxide semiconductor film having low resistance is formed and the resistance of a channel region of the oxide semiconductor film is increased. Note that an oxide semiconductor film is subjected to a process for reducing the resistance to have low resistance. The process for reducing the resistance of the oxide semiconductor film may be a laser process or heat treatment at a temperature higher than or equal to 450° C. and lower than or equal to 740° C., for example. A process for increasing the resistance of the channel region of the oxide semiconductor film having low resistance may be performed by plasma oxidation or implantation of oxygen ions, for example.

Abstract translation: 提供具有稳定电特性的包括氧化物半导体膜的晶体管。 还提供了具有优异的导通状态特性的包括氧化物半导体膜的晶体管。 其中形成具有低电阻的氧化物半导体膜并且氧化物半导体膜的沟道区的电阻增加的半导体器件。 注意，氧化物半导体膜经受用于降低电阻以降低电阻的工艺。 用于降低氧化物半导体膜的电阻的方法可以是例如在高于或等于450℃且低于或等于740℃的温度下的激光处理或热处理。 例如，可以通过等离子体氧化或氧离子的注入来提高具有低电阻的氧化物半导体膜的沟道区域的电阻的方法。