公开(公告)号：US10910407B2

公开(公告)日：2021-02-02

申请号：US16478244

申请日：2018-01-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshinori Ando ,  Takashi Hamada ,  Yasumasa Yamane

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786

Abstract: A high-performance semiconductor device is provided. The semiconductor device includes a transistor, an insulating film over the transistor, an electrode, and a metal oxide over the insulating film. The transistor includes a first gate electrode, a first gate insulating film over the first gate electrode, an oxide over the first gate insulating film, a source electrode and a drain electrode electrically connected to the oxide, a second gate insulating film over the oxide, and a second gate electrode over the second gate insulating film. The electrode includes a region in contact with the insulating film. The first gate insulating film is in contact with the insulating film. The thicknesses of the insulating film over the second gate electrode, the insulating film over the source electrode, and the insulating film over the drain electrode are substantially the same, and the insulating film includes excess oxygen.

公开(公告)号：US10043914B2

公开(公告)日：2018-08-07

申请号：US15175183

申请日：2016-06-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Motomu Kurata ,  Shinya Sasagawa ,  Taiga Muraoka ,  Hiroaki Honda ,  Takashi Hamada

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L29/417

Abstract: A substrate having an insulating surface is prepared; a stacked film including a first oxide semiconductor layer and a second oxide semiconductor layer is formed over the substrate; a mask layer is formed over part of the stacked film and then dry etching treatment is performed, so that the stacked film is removed, with a region provided with the mask layer remaining, and a reaction product is formed on a side surface of the remaining stacked film; the reaction product is removed by wet etching treatment after removal of the mask layer; a source electrode and a drain electrode are formed over the stacked film; and a third oxide semiconductor layer, a gate insulating film, and a gate electrode are stacked and formed in this order over the stacked film, and the source electrode and the drain electrode.

公开(公告)号：US20180197997A1

公开(公告)日：2018-07-12

申请号：US15864033

申请日：2018-01-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daigo ITO ,  Daisuke Matsubayashi ,  Masaharu Nagai ,  Yoshiaki Yamamoto ,  Takashi Hamada ,  Yutaka Okazaki ,  Shinya Sasagawa ,  Motomu Kurata ,  Naoto Yamade

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/425 ,  H01L21/46 ,  H01L27/12

CPC classification number: H01L29/78693 ,  H01L21/425 ,  H01L21/46 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7782 ,  H01L29/7854 ,  H01L29/7855 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).

公开(公告)号：US09935203B2

公开(公告)日：2018-04-03

申请号：US15696231

申请日：2017-09-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya Sasagawa ,  Takashi Hamada ,  Akihisa Shimomura ,  Satoru Okamoto ,  Katsuaki Tochibayashi

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L21/465 ,  H01L21/4757 ,  H01L29/423 ,  H01L21/4763

CPC classification number: H01L29/7869 ,  H01L21/465 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/42372 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78648

Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a high on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device having a high degree of integration is provided. A semiconductor device including an oxide semiconductor; a second insulator; a second conductor; a third conductor; a fourth conductor; a fifth conductor; a first conductor and a first insulator embedded in an opening portion formed in the second insulator, the second conductor, the third conductor, the fourth conductor, and the fifth conductor; a region where a side surface and a bottom surface of the second conductor are in contact with the fourth conductor; and a region where a side surface and a bottom surface of the third conductor are in contact with the fifth conductor.

公开(公告)号：US09871145B2

公开(公告)日：2018-01-16

申请号：US15628699

申请日：2017-06-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daigo Ito ,  Daisuke Matsubayashi ,  Masaharu Nagai ,  Yoshiaki Yamamoto ,  Takashi Hamada ,  Yutaka Okazaki ,  Shinya Sasagawa ,  Motomu Kurata ,  Naoto Yamade

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/786 ,  H01L29/66 ,  H01L21/425 ,  H01L21/46 ,  H01L27/12

CPC classification number: H01L29/78693 ,  H01L21/425 ,  H01L21/46 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7782 ,  H01L29/7854 ,  H01L29/7855 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).

公开(公告)号：US08906714B2

公开(公告)日：2014-12-09

申请号：US13744995

申请日：2013-01-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Takashi Hamada ,  Satoshi Seo

IPC: H01L21/00 ,  H01L33/00 ,  H01L51/00 ,  H01L27/32 ,  H01L51/56

CPC classification number: H01L33/005 ,  H01L27/3211 ,  H01L51/0005 ,  H01L51/0021 ,  H01L51/56 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a light emitting device is provided which requires low cost, is easy, and has high throughput. The method of manufacturing a light emitting device is characterized in that: a solution containing a light emitting material is ejected to an anode or cathode under reduced pressure; a solvent in the solution is volatilized until the solution reaches the anode or cathode; and the remaining light emitting material is deposited on the anode or cathode to form a light emitting layer. A burning step for reduction in film thickness is not required after the solution application. Therefore, the manufacturing method, which requires low cost and is easy but which has high throughput, can be provided.

Abstract translation: 提供一种制造发光器件的方法，其需要低成本，容易并且具有高生产量。 制造发光器件的方法的特征在于：将含有发光材料的溶液在减压下喷射到阳极或阴极; 溶液中的溶剂挥发，直到溶液到达阳极或阴极; 并且剩余的发光材料沉积在阳极或阴极上以形成发光层。 在施加溶液后，不需要用于降低膜厚度的燃烧步骤。 因此，可以提供需要低成本且容易但具有高生产量的制造方法。

公开(公告)号：US12068198B2

公开(公告)日：2024-08-20

申请号：US17605187

申请日：2020-04-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Tsutomu Murakawa ,  Shinya Sasagawa ,  Naoto Yamade ,  Takashi Hamada ,  Hiroki Komagata

IPC: H01L21/8234 ,  H01L21/225 ,  H01L21/28 ,  H01L29/66 ,  H01L27/088 ,  H01L29/786

CPC classification number: H01L21/823412 ,  H01L21/2253 ,  H01L21/28185 ,  H01L29/6675 ,  H01L27/088 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a semiconductor device with less variations, a first insulator is deposited; a stack of first and a second oxides and a first conductor is formed over the first insulator; a second insulator is formed over the first insulator and the stack; an opening is formed in the second insulator; a top surface of the second oxide is exposed by removing a region of the first conductor, second and third conductors are formed over the second oxide, and then cleaning treatment is performed; a first oxide film is deposited in contact with a side surface of the first oxide and top and side surfaces of the second oxide; heat treatment is performed on an interface between the second oxide and the first oxide film through the first oxide film; and the second insulator is exposed and a fourth conductor, a third insulator, and a third oxide are formed in the opening.

公开(公告)号：US11372276B2

公开(公告)日：2022-06-28

申请号：US17123392

申请日：2020-12-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yoshiharu Hirakata ,  Tetsuji Ishitani ,  Daisuke Kubota ,  Ryo Hatsumi ,  Masaru Nakano ,  Takashi Hamada

IPC: G02F1/1333

Abstract: A display device including a peripheral circuit portion with high operation stability. The display device includes a first substrate and a second substrate. A first insulating layer is on a first plane of the first substrate, and a second insulating layer is on a first plane of the second substrate. An area of the first plane of the first substrate is the same as an area of the first plane of the second substrate. The first plane of the first substrate and the first plane of the second substrate face each other. A bonding layer is between the first insulating layer and the second insulating layer. A protection film is in contact with the first substrate, the first insulating layer, the bonding layer, the second insulating layer, and the second substrate.

公开(公告)号：US10141452B2

公开(公告)日：2018-11-27

申请号：US15864033

申请日：2018-01-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daigo Ito ,  Daisuke Matsubayashi ,  Masaharu Nagai ,  Yoshiaki Yamamoto ,  Takashi Hamada ,  Yutaka Okazaki ,  Shinya Sasagawa ,  Motomu Kurata ,  Naoto Yamade

IPC: H01L29/786 ,  H01L21/46 ,  H01L27/12 ,  H01L29/66 ,  H01L21/425 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/24 ,  H01L29/778

Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).

公开(公告)号：US09882061B2

公开(公告)日：2018-01-30

申请号：US15070320

申请日：2016-03-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Satoshi Toriumi ,  Takashi Hamada

IPC: H01L21/28 ,  H01L21/477 ,  H01L29/786 ,  H01L29/66 ,  H01L29/04 ,  H01L21/02 ,  H01L23/528 ,  H01L23/522 ,  H01L27/12 ,  H01L27/146

CPC classification number: H01L29/7869 ,  H01L21/02211 ,  H01L21/28158 ,  H01L21/477 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1225 ,  H01L27/14616 ,  H01L27/14632 ,  H01L29/045 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78696

Abstract: A transistor with favorable electrical characteristics is provided. A minute transistor is provided. Provided is a semiconductor device including a first insulator over a substrate, a second insulator over the first insulator, a semiconductor over the second insulator, a first conductor and a second conductor over the semiconductor, a third insulator over the semiconductor, a fourth insulator over the third insulator, a third conductor over the fourth insulator, and a fifth insulator over the first insulator, the first conductor, and the second conductor. In the semiconductor device, the second insulator and the third insulator each include at least one element other than oxygen included in the semiconductor, respectively, and the semiconductor includes a region having a carbon concentration of 3×1018 atoms/cm3 or lower.