公开(公告)号：US11467909B1

公开(公告)日：2022-10-11

申请号：US17506953

申请日：2021-10-21

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Dae Sik Park

IPC: G06F11/07 ,  G06F11/14 ,  G06F13/42 ,  G06F11/30

Abstract: A Peripheral Component Interconnect Express (PCIe) interface device coupled to an external device through a link including a plurality of lanes according to the present disclosure includes an EQ controller controlling the PCIe interface device to perform an equalization operation for determining a transmitter or receiver setting of each of the plurality of lanes, and an EQ information storage storing log information indicating a number of equalization operation attempts with respect to each of a plurality of EQ coefficients and storing error information about an error occurring in an LO state with respect to each of the plurality of EQ coefficients, which includes a transmitter coefficient or a receiver coefficient, wherein the EQ controller determines a final EQ coefficient using the log information and the error information.

公开(公告)号：US11960424B2

公开(公告)日：2024-04-16

申请号：US17522843

申请日：2021-11-09

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon

IPC: G06F13/28 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F13/4221 ,  G06F2213/0026

Abstract: A device may include a lane group, a command queue, and a link manager. The lane group may include a first lane and at least one or more second lanes to form a link for communicating with a host. The command queue may store commands for at least one direct memory access (DMA) device, the commands generated based on a request of the host. The link manager may, in response to detecting an event that an amount of the commands stored in the command queue being less than or equal to a reference value, change an operation mode from a first power mode to a second power mode in which power consumption is less than that of the first power mode, deactivate the at least one or more second lanes, and provide a second operation clock lower than a first operation clock to the at least one DMA device.

公开(公告)号：US11809344B2

公开(公告)日：2023-11-07

申请号：US17527032

申请日：2021-11-15

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon

IPC: G06F13/16 ,  G06F13/28 ,  G06F13/42 ,  G06F11/07

CPC classification number: G06F13/1684 ,  G06F11/0772 ,  G06F13/1689 ,  G06F13/28 ,  G06F13/4221 ,  G06F2213/0026

Abstract: A Peripheral Component Interconnect Express (PCIe) interface device includes a PCIe layer and a PCIe controller. The PCIe layer performs communication between a host and a Direct Memory Access (DMA) device. The PCIe controller switches an operating clock from a PCIe clock generated based on a reference clock to an internal clock, processes data of the PCIe layer on the basis of the internal clock, and recovers a link with respect to the host, when a reset signal received from the host is asserted or the reference clock is off.

公开(公告)号：US11797468B2

公开(公告)日：2023-10-24

申请号：US17506889

申请日：2021-10-21

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon

IPC: G06F13/42 ,  G06F11/20

CPC classification number: G06F13/4221 ,  G06F11/2007 ,  G06F2213/0026

Abstract: A PCIe device setting, when a fail lane is detected during a link setting operation, a link by using remaining lanes includes a plurality of lanes comprising a plurality of ports, and a link controller setting a link including the plurality of lanes, wherein the link is set to have a link width that includes remaining lanes, except for a fail lane from among the plurality of lanes, wherein the fail lane from among the plurality of lanes has a state in which the fail lane is unable to form a link with remaining lanes that have not failed from among the plurality of lanes.

公开(公告)号：US11782497B2

公开(公告)日：2023-10-10

申请号：US17522827

申请日：2021-11-09

Applicant: SK hynix Inc.

Inventor： Ji Woon Yang ,  Yong Tae Jeon

IPC: G06F1/3234 ,  G06F13/42 ,  G06F13/40 ,  G06F1/3206 ,  G06F9/4401

CPC classification number: G06F1/3253 ,  G06F1/3206 ,  G06F13/4022 ,  G06F13/4282 ,  G06F9/4418 ,  G06F2213/0026 ,  Y02D10/00

Abstract: A peripheral component interconnect express (PCIe) interface device is provided to include: a root complex configured to support a PCIe port, a memory connected to an input/output structure through the root complex, a switch connected to the root complex through a link and configured to transmit a transaction, and an end point connected to the switch through the link to transmit and receive a packet. The PCIe interface device may perform a link power management by changing a state of the link in response to a detection of an idle state of the link.

公开(公告)号：US20230318606A1

公开(公告)日：2023-10-05

申请号：US17958554

申请日：2022-10-03

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Ki Chul Noh

IPC: H03K19/173 ,  H03K19/17728 ,  G06F13/42 ,  G06F13/364

CPC classification number: H03K19/1737 ,  G06F13/364 ,  G06F13/4221 ,  H03K19/17728

Abstract: Provided herein may be an interface device and a method of operating the same. The interface device may include a first port configured to enable communication with a host, a second port configured to enable communication with the host, and a function manager including a plurality of variable functions that are selectively assignable to at least one of the first port and the second port.

公开(公告)号：US11741039B2

公开(公告)日：2023-08-29

申请号：US17467078

申请日：2021-09-03

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon

IPC: G06F13/36 ,  G06F13/42

CPC classification number: G06F13/4221 ,  G06F2213/0026

Abstract: A PCIe device and a method of operating the same are provided. The PCIe device may include a throughput calculator configured to calculate a throughput of each of a plurality of functions, a throughput analysis information generator configured to generate throughput analysis information indicating a result of a comparison between a throughput limit and the calculated throughput, a delay time information generator configured to generate a delay time for delaying a command fetch operation for each function based on the throughput analysis information, a command lookup table storage configured to store command-related information and a delay time of a function corresponding to a target command, the command-related information including information related to the target command to be fetched from a host, and a command fetcher configured to fetch the target command based on the command-related information and the delay time of the corresponding function.

公开(公告)号：US11726870B2

公开(公告)日：2023-08-15

申请号：US17380593

申请日：2021-07-20

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Gil Bong Park ,  Dong Jin Seong

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/07 ,  G06F9/448 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F11/1068 ,  G06F9/4498 ,  G06F11/0757 ,  G06F13/4027 ,  G06F13/4221

Abstract: Provided herein is a PCIe interface device. The PCIe interface device may include a NOP DLLP generator configured to generate a No Operation (NOP) data link layer packet (DLLP) including event information representing an event in response to the occurrence of the event and a transmitter configured to transmit the NOP DLLP to an external device through a link including a plurality of lanes.

公开(公告)号：US20220309014A1

公开(公告)日：2022-09-29

申请号：US17467070

申请日：2021-09-03

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Ji Woon Yang ,  Sang Hyun Yoon ,  Se Hyeon Han

IPC: G06F13/24 ,  G06F13/42

Abstract: Provided are a Peripheral Component Interconnect Express (PCIe) interface device and a method of operating the same. The PCIe interface device may include a performance analyzer and a traffic class controller. The performance analyzer may be configured to measure throughputs of multiple functions executed on one or more Direct Memory Access (DMA) devices. The traffic class controller may be configured to allocate traffic class values to transaction layer packets received from the multiple functions based on the throughputs of the multiple functions.

公开(公告)号：US11995019B2

公开(公告)日：2024-05-28

申请号：US17504351

申请日：2021-10-18

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Byung Cheol Kang ,  Seung Duk Cho

IPC: G06F13/42 ,  G06F12/06 ,  G06F13/10 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F12/0653 ,  G06F13/105 ,  G06F13/4022

Abstract: A peripheral component interconnect express (PCIe) device includes a plurality of common functions performing operations associated with a PCIe interface according to a function type of each of the plurality of common functions, each of the plurality of common functions being programmable to be a function type selected from a plurality function types, and a function type controller determining the function type of each of the plurality of common functions based on function type setting information provided from a host. Each function type may be a physical function type, a virtual function type, or a disable function type.