公开(公告)号：US20190181270A1

公开(公告)日：2019-06-13

申请号：US16228620

申请日：2018-12-20

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/12 ,  H01L29/06 ,  H01L29/41 ,  H01L29/775 ,  H01L27/092 ,  H01L29/778 ,  H01L29/417 ,  H01L29/40

Abstract: Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.

公开(公告)号：US10319630B2

公开(公告)日：2019-06-11

申请号：US13629411

申请日：2012-09-27

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu

IPC: H01L23/48 ,  H01L23/52 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A plurality of metal tracks are formed in a plurality of intermetal dielectric layers stacked in an integrated circuit die. Thin protective dielectric layers are formed around the metal tracks. The protective dielectric layers act as a hard mask to define contact vias between metal tracks in the intermetal dielectric layers.

公开(公告)号：US10103245B2

公开(公告)日：2018-10-16

申请号：US15664225

申请日：2017-07-31

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Pietro Montanini

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/165

Abstract: An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress into the channel regions of the NMOS transistors and compressive stress into the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.

公开(公告)号：US10084080B2

公开(公告)日：2018-09-25

申请号：US14675298

申请日：2015-03-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/78 ,  H01L29/165 ,  H01L29/267 ,  H01L29/739 ,  H01L27/092 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/7827 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/267 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/66356 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/785

Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

公开(公告)号：US20180261679A1

公开(公告)日：2018-09-13

申请号：US15981659

申请日：2018-05-16

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L29/51 ,  H01L21/02 ,  C23C14/04 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L29/51 ,  C23C14/048 ,  C23C14/221 ,  H01L21/02521 ,  H01L21/02631 ,  H01L21/28088 ,  H01L21/285 ,  H01L21/2855 ,  H01L21/76831 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Energy bands of a thin film containing molecular clusters are tuned by controlling the size and the charge of the clusters during thin film deposition. Using atomic layer deposition, an ionic cluster film is formed in the gate region of a nanometer-scale transistor to adjust the threshold voltage, and a neutral cluster film is formed in the source and drain regions to adjust contact resistance. A work function semiconductor material such as a silver bromide or a lanthanum oxide is deposited so as to include clusters of different sizes such as dimers, trimers, and tetramers, formed from isolated monomers. A type of Atomic Layer Deposition system is used to deposit on semiconductor wafers molecular clusters to form thin film junctions having selected energy gaps. A beam of ions contains different ionic clusters which are then selected for deposition by passing the beam through a filter in which different apertures select clusters based on size and orientation.

公开(公告)号：US20180226511A1

公开(公告)日：2018-08-09

申请号：US15945937

申请日：2018-04-05

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Yiheng Xu ,  John H. Zhang

IPC: H01L29/786 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/24 ,  H01L27/146 ,  H01L29/66

Abstract: Processes and overturned thin film device structures generally include a metal gate having a concave shape defined by three faces. The processes generally include forming the overturned thin film device structures such that the channel self-aligns to the metal gate and the contacts can be self-aligned to the sacrificial material.

公开(公告)号：US10002938B2

公开(公告)日：2018-06-19

申请号：US14464604

申请日：2014-08-20

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L21/8234 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/45 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/768 ,  C23C14/04 ,  C23C14/22 ,  H01L29/66

CPC classification number: H01L29/51 ,  C23C14/048 ,  C23C14/221 ,  H01L21/02521 ,  H01L21/02631 ,  H01L21/28088 ,  H01L21/285 ,  H01L21/2855 ,  H01L21/76831 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Energy bands of a thin film containing molecular clusters are tuned by controlling the size and the charge of the clusters during thin film deposition. Using atomic layer deposition, an ionic cluster film is formed in the gate region of a nanometer-scale transistor to adjust the threshold voltage, and a neutral cluster film is formed in the source and drain regions to adjust contact resistance. A work function semiconductor material such as a silver bromide or a lanthanum oxide is deposited so as to include clusters of different sizes such as dimers, trimers, and tetramers, formed from isolated monomers. A type of Atomic Layer Deposition system is used to deposit on semiconductor wafers molecular clusters to form thin film junctions having selected energy gaps. A beam of ions contains different ionic clusters which are then selected for deposition by passing the beam through a filter in which different apertures select clusters based on size and orientation.

公开(公告)号：US20180144926A1

公开(公告)日：2018-05-24

申请号：US15874654

申请日：2018-01-18

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Yann Mignot ,  Lawrence A. Clevenger ,  Carl Radens ,  Richard Stephen Wise ,  Yiheng Xu ,  Yannick Loquet ,  Hsueh-Chung Chen

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/0217 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect process incorporates air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of an air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the air gap is used as an insulator between adjacent metal lines, while a ULK film is retained to insulate vias. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

公开(公告)号：US20180068994A1

公开(公告)日：2018-03-08

申请号：US15802541

申请日：2017-11-03

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Yiheng Xu ,  John H. Zhang

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L25/18 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15156 ,  H01L2924/15313 ,  H01L2924/157

Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the first stair, wherein the at least one additional chip is vertically spaced apart from the first chip.

公开(公告)号：US09905648B2

公开(公告)日：2018-02-27

申请号：US14175308

申请日：2014-02-07

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L29/66 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/10 ,  H01L29/786 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78684 ,  H01L29/78696

Abstract: Transistors having partially recessed gates are constructed on silicon-on-insulator (SOI) semiconductor wafers provided with a buried oxide layer (BOX), for example, FD-SOI and UTBB devices. An epitaxially grown channel region relaxes constraints on the design of doped source and drain profiles. Formation of a partially recessed gate and raised epitaxial source and drain regions allow further improvements in transistor performance and reduction of short channel effects such as drain induced barrier lowering (DIBL) and control of a characteristic subthreshold slope. Gate recess can be varied to place the channel at different depths relative to the dopant profile, assisted by advanced process control. The partially recessed gate has an associated high-k gate dielectric that is initially formed in contact with three sides of the gate. Subsequent removal of the high-k sidewalls and substitution of a lower-k silicon nitride encapsulant lowers capacitance between the gate and the source and drain regions.