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    Transistor having a stressed body
    14.
    发明授权
    Transistor having a stressed body 有权
    具有受压体的晶体管

    公开(公告)号：US09123809B2

    公开(公告)日：2015-09-01

    申请号：US14494979

    申请日：2014-09-24

    Applicant: STMicroelectronics, Inc.

    Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

    IPC: H01L29/76 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L21/266 ,  H01L21/762 ,  H01L29/06

    CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/66628 ,  H01L29/7849

    Abstract: A transistor includes a body and a semiconductor region configured to stress a portion of the body. For example, stressing a channel of the transistor may increase the mobility of carriers in the channel, and thus may reduce the “on” resistance of the transistor. For example, the substrate, source/drain regions, or both the substrate and source/drain regions of a PFET may be doped to compressively stress the channel so as to increase the mobility of holes in the channel. Or, the substrate, source/drain regions, or both the substrate and source/drain regions of an NFET may be doped to tensile stress the channel so as to increase the mobility of electrons in the channel.

    Abstract translation: 晶体管包括主体和构造成对身体的一部分施加应力的半导体区域。 例如，施加晶体管的沟道可以增加沟道中载流子的迁移率，从而可以降低晶体管的“导通”电阻。 例如，可以掺杂PFET的衬底，源极/漏极区域或者衬底和源/漏极区域，以对沟道进行压缩应力，从而增加沟道中空穴的迁移率。 或者，可以掺杂NFET的衬底，源极/漏极区域或衬底和源极/漏极区域两者以使通道拉伸应力，以增加沟道中电子的迁移率。

    Method of making a semiconductor device including an all around gate
    15.
    发明授权
    Method of making a semiconductor device including an all around gate 有权
    制造包括全周围栅极的半导体器件的方法

    公开(公告)号：US09082788B2

    公开(公告)日：2015-07-14

    申请号：US13906702

    申请日：2013-05-31

    Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Nicolas Loubet ,  Prasanna Khare ,  Huiming Bu

    IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/78

    CPC classification number: H01L29/66484 ,  H01L21/823481 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

    Abstract: A method of making a semiconductor device includes forming an intermediate structure including second semiconductor fin portions above a first semiconductor layer, and top first semiconductor fin portions extending from respective ones of the second semiconductor fin portions. The second semiconductor fin portions are selectively etchable with respect to the top first semiconductor fin portions. A dummy gate is on the intermediate structure. The second semiconductor fin portions are selectively etched to define bottom openings under respective ones of the top first semiconductor fin portions. The bottom openings are filled with a dielectric material.

    Abstract translation: 制造半导体器件的方法包括在第一半导体层之上形成包括第二半导体鳍部的中间结构以及从第二半导体鳍部中的相应半导体鳍部延伸的顶部第一半导体鳍部。 第二半导体鳍片部分相对于顶部第一半导体鳍片部分可选择性地蚀刻。 虚拟门在中间结构上。 选择性地蚀刻第二半导体鳍片部分以在顶部第一半导体鳍片部分的相应一个下限定底部开口。 底部开口填充有电介质材料。

    Memory device having multiple dielectric gate stacks and related methods
    16.
    发明授权
    Memory device having multiple dielectric gate stacks and related methods 有权
    具有多个介电栅极堆叠的存储器件及相关方法

    公开(公告)号：US09006816B2

    公开(公告)日：2015-04-14

    申请号：US13852645

    申请日：2013-03-28

    Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

    Inventor： Prasanna Khare ,  Stephane Allegret-Maret ,  Nicolas Loubet ,  Qing Liu ,  Hemanth Jagannathan ,  Lisa Edge ,  Kangguo Cheng ,  Bruce Doris

    IPC: H01L29/792 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115

    CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack. The gate stack may include a first dielectric layer over the channel region, a first diffusion barrier layer over the first dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second dielectric layer over the first electrically conductive layer, a second diffusion barrier layer over the second dielectric layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.

    Abstract translation: 存储器件可以包括半导体衬底和半导体衬底中的存储晶体管。 存储晶体管可以包括半导体衬底中的源极和漏极区域以及它们之间的沟道区域和栅极堆叠。 栅极堆叠可以包括沟道区域上的第一介电层，第一介电层上的第一扩散阻挡层，第一扩散阻挡层上的第一导电层，第一导电层上的第二介电层，第二介电层 第二介电层上的扩散阻挡层，以及位于第二扩散阻挡层上的第二导电层。 第一和第二电介质层可以包括不同的电介质材料，并且第一扩散阻挡层可以比第二扩散阻挡层薄。

    FinFET device with isolated channel
    17.
    发明授权
    FinFET device with isolated channel 有权
    FinFET器件具有隔离通道

    公开(公告)号：US08759874B1

    公开(公告)日：2014-06-24

    申请号：US13691070

    申请日：2012-11-30

    Applicant: STMicroelectronics, Inc.

    Inventor： Nicolas Loubet ,  Prasanna Khare

    IPC: H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

    CPC classification number: H01L27/088 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/785

    Abstract: Despite improvements in FinFETs and strained silicon devices, transistors continue to suffer performance degradation as device dimensions shrink. These include, in particular, leakage of charge between the semiconducting channel and the substrate. An isolated channel FinFET device prevents channel-to-substrate leakage by inserting an insulating layer between the channel (fin) and the substrate. The insulating layer isolates the fin from the substrate both physically and electrically. To form the isolated FinFET device, an array of bi-layer fins can be grown epitaxially from the silicon surface, between nitride columns that provide localized insulation between adjacent fins. Then, the lower fin layer can be removed, while leaving the upper fin layer, thus yielding an interdigitated array of nitride columns and semiconducting fins suspended above the silicon surface. A resulting gap underneath the upper fin layer can then be filled in with oxide to isolate the array of fin channels from the substrate.

    Abstract translation: 尽管FinFET和应变硅器件有所改进，晶体管在器件尺寸缩小的同时仍继续受到性能的降低。 这些特别包括在半导体沟道和衬底之间的电荷泄漏。 隔离沟道FinFET器件通过在沟道（鳍片）和衬底之间插入绝缘层来防止沟道对衬底的泄漏。 绝缘层物理和电气都将鳍片与衬底隔离开来。 为了形成隔离的FinFET器件，可以从硅表面，在提供相邻鳍片之间的局部绝缘的氮化物柱之间外延生长双层鳍片阵列。 然后，可以除去下部翅片层，同时留下上部翅片层，从而产生悬挂在硅表面上方的氮化物柱和半导体翅片的交错排列。 然后可以用氧化物填充在上翅片层下方的产生的间隙，以将翅片通道阵列与基底隔离。

    FINFET DEVICE WITH ISOLATED CHANNEL
    18.
    发明申请
    FINFET DEVICE WITH ISOLATED CHANNEL 有权
    具有隔离通道的FINFET器件

    公开(公告)号：US20140151746A1

    公开(公告)日：2014-06-05

    申请号：US13691070

    申请日：2012-11-30

    Applicant: STMICROELECTRONICS, INC.

    Inventor： Nicolas Loubet ,  Prasanna Khare

    IPC: H01L27/088 ,  H01L29/66

    CPC classification number: H01L27/088 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/785

    Abstract: Despite improvements in FinFETs and strained silicon devices, transistors continue to suffer performance degradation as device dimensions shrink. These include, in particular, leakage of charge between the semiconducting channel and the substrate. An isolated channel FinFET device prevents channel-to-substrate leakage by inserting an insulating layer between the channel (fin) and the substrate. The insulating layer isolates the fin from the substrate both physically and electrically. To form the isolated FinFET device, an array of bi-layer fins can be grown epitaxially from the silicon surface, between nitride columns that provide localized insulation between adjacent fins. Then, the lower fin layer can be removed, while leaving the upper fin layer, thus yielding an interdigitated array of nitride columns and semiconducting fins suspended above the silicon surface. A resulting gap underneath the upper fin layer can then be filled in with oxide to isolate the array of fin channels from the substrate.

    Abstract translation: 尽管FinFET和应变硅器件有所改进，晶体管在器件尺寸缩小的同时仍继续受到性能的降低。 这些特别包括在半导体沟道和衬底之间的电荷泄漏。 隔离沟道FinFET器件通过在沟道（鳍片）和衬底之间插入绝缘层来防止沟道对衬底的泄漏。 绝缘层物理和电气都将鳍片与衬底隔离开来。 为了形成隔离的FinFET器件，可以从硅表面，在提供相邻鳍片之间的局部绝缘的氮化物柱之间外延生长双层鳍片阵列。 然后，可以除去下部翅片层，同时留下上部翅片层，从而产生悬挂在硅表面上方的氮化物柱和半导体翅片的交错排列。 然后可以用氧化物填充在上翅片层下方的产生的间隙，以将翅片通道阵列与基底隔离。

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