公开(公告)号：US09991000B2

公开(公告)日：2018-06-05

申请号：US15476618

申请日：2017-03-31

Applicant: STMicroelectronics S.r.l.

Inventor： Emanuela Calvetti ,  Marcella Carissimi ,  Marco Pasotti

IPC: G11C11/00 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34 ,  G11C16/10 ,  G11C13/00 ,  G11C11/16

CPC classification number: G11C16/24 ,  G11C7/065 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1673 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0033 ,  G11C13/0035 ,  G11C13/004 ,  G11C13/0064 ,  G11C16/10 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3427 ,  G11C16/349 ,  G11C2013/0042 ,  G11C2013/0054 ,  G11C2013/0066

Abstract: In accordance with an embodiment, a circuit includes a sense amplifier circuit configured to sense a difference between a first current based on a direct memory bit and a second current based on a complementary memory bit. The direct memory bit is coupled to a first input of the sense amplifier circuit, and the complementary memory bit is coupled to a second input of the sense amplifier circuit. A controller is configured to, during a sense operation, selectively add a first margin current to the first current, and during the sense operation, selectively add a second margin current to the second current.

公开(公告)号：US20180040380A1

公开(公告)日：2018-02-08

申请号：US15476618

申请日：2017-03-31

Applicant: STMicroelectronics S.r.l.

Inventor： Emanuela Calvetti ,  Marcella Carissimi ,  Marco Pasotti

IPC: G11C16/24 ,  G11C11/16 ,  G11C16/10 ,  G11C13/00 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/24 ,  G11C7/065 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1673 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0033 ,  G11C13/0035 ,  G11C13/004 ,  G11C13/0064 ,  G11C16/10 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3427 ,  G11C16/349 ,  G11C2013/0042 ,  G11C2013/0054 ,  G11C2013/0066

Abstract: In accordance with an embodiment, a circuit includes a sense amplifier circuit configured to sense a difference between a first current based on a direct memory bit and a second current based on a complementary memory bit. The direct memory bit is coupled to a first input of the sense amplifier circuit, and the complementary memory bit is coupled to a second input of the sense amplifier circuit. A controller is configured to, during a sense operation, selectively add a first margin current to the first current, and during the sense operation, selectively add a second margin current to the second current.

公开(公告)号：US20170178722A1

公开(公告)日：2017-06-22

申请号：US15422290

申请日：2017-02-01

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： Marco Pasotti ,  Marcella Carissimi ,  Rajat Kulshrestha ,  Chantal AURICCHIO

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/065 ,  G11C7/08 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0097 ,  G11C2013/0042 ,  G11C2207/002

Abstract: A memory device includes an array of phase-change memory (PCM) cells and complementary PCM cells. A column decoder is coupled to the array of PCM cells and complementary PCM cells, and a sense amplifier is coupled to the column decoder. The sense amplifier includes a current integrator configured to receive first and second currents of a given PCM cell and complementary PCM cell, respectively. A current-to-voltage converter is coupled to the current integrator and is configured to receive the first and second currents, and to provide first and second voltages of the given PCM cell and complementary PCM cell to first and second nodes, respectively. A logic circuit is coupled to the first and second nodes and is configured to disable the column decoder and to discharge the bitline and complementary bitline voltages in response to the first and second voltages.

公开(公告)号：US12260910B2

公开(公告)日：2025-03-25

申请号：US18148380

申请日：2022-12-29

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Fabio Enrico Carlo Disegni ,  Marcella Carissimi ,  Alessandro Tomasoni ,  Daniele Lo Iacono

IPC: G11C13/00

Abstract: The present disclosure is directed to a sense amplifier architecture for a memory device having a plurality of memory cells. Groups of non-volatile memory cells store respective codewords formed by stored logic states, logic high or logic low, of the memory cells of the group. The sense amplifier architecture has a plurality of sense amplifier reading branches, each sense amplifier reading branch coupled to a respective memory cell and configured to provide an output signal, which is indicative of a cell current flowing through the same memory cell; a comparison stage, to perform a comparison between the cell currents of memory cells of a group; and a logic stage, to determine, based on comparison results provided by the comparison stage, a read codeword corresponding to the group of memory cells. Information may be stored in different subsets of codewords, the sense amplifier architecture in this case having a subset definition circuit, to allow a preliminary determination of the subset to which a codeword to be read belongs to, based on reference signals.

公开(公告)号：US11942144B2

公开(公告)日：2024-03-26

申请号：US17582675

申请日：2022-01-24

Applicant: STMicroelectronics S.r.l. ,  Alma Mater Studiorum—Universita' Di Bologna

Inventor： Marco Pasotti ,  Marcella Carissimi ,  Antonio Gnudi ,  Eleonora Franchi Scarselli ,  Alessio Antolini ,  Andrea Lico

IPC: G11C11/4096 ,  G06F7/544 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4094

CPC classification number: G11C11/4096 ,  G06F7/5443 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4094

Abstract: A circuit includes a memory array with memory cells arranged in a matrix of rows and columns, where each row includes a word line connected to the memory cells of the row, and each column includes a bit line connected to the memory cells of the column. Computational weights for an in-memory compute operation (IMCO) are stored in the memory cells. A word line control circuit simultaneously actuates word lines in response to input signals providing coefficient data for the IMCO by applying word line signal pulses. A column processing circuit connected to the bit lines processes analog signals developed on the bit lines in response to the simultaneous actuation of the word lines to generate multiply and accumulate output signals for the IMCO. Pulse widths of the signal pulses are modulated to compensate for cell drift. The IMCO further handles positive/negative calculation for the coefficient data and computational weights.

公开(公告)号：US11798630B2

公开(公告)日：2023-10-24

申请号：US17407903

申请日：2021-08-20

Applicant: STMicroelectronics S.r.l.

Inventor： Marcella Carissimi ,  Fabio Enrico Carlo Disegni ,  Chantal Auricchio ,  Cesare Torti ,  Davide Manfre' ,  Laura Capecchi ,  Emanuela Calvetti ,  Stefano Zanchi

IPC: G11C16/28 ,  G11C16/10 ,  G11C7/04 ,  G11C16/24 ,  G11C16/30

CPC classification number: G11C16/102 ,  G11C7/04 ,  G11C16/24 ,  G11C16/28 ,  G11C16/30

Abstract: A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.

公开(公告)号：US11189343B2

公开(公告)日：2021-11-30

申请号：US16940837

申请日：2020-07-28

Applicant: STMicroelectronics S.r.l.

Inventor： Laura Capecchi ,  Marco Pasotti ,  Marcella Carissimi ,  Riccardo Zurla

IPC: G11C5/14 ,  G11C13/00 ,  G05F3/26

Abstract: A current-generator circuit includes an output-current generator circuit having a control branch to be coupled to a control current generator and adapted to provide a control current pulse and a driver electrically coupled between the control branch and the output leg. A compensation circuit includes a first compensation branch configured to generate a compensation current pulse that is a function of the control current pulse and a second compensation branch coupled in a current mirror configuration with the first compensation branch to receive the compensation current pulse. The second compensation branch includes a resistive block having an electrical resistance that is a function of a resistance of an output load. The second compensation branch is electrically coupled to the control branch and the driver is electrically coupled to the control branch and to the output leg.

公开(公告)号：US11133064B2

公开(公告)日：2021-09-28

申请号：US16931335

申请日：2020-07-16

Applicant: STMicroelectronics S.r.l.

Inventor： Marcella Carissimi ,  Laura Capecchi ,  Marco Pasotti ,  Fabio Enrico Carlo Disegni

IPC: G11C7/02 ,  G11C13/00

Abstract: A sense amplifier and a method for accessing a memory device are disclosed. In an embodiment a sense amplifier for a memory device includes a first input node selectively coupled to a first memory cell through a first local bitline and a first main bitline, a second input node selectively coupled through a second local bitline and a second main bitline to a second memory cell or to a reference generator configured to generate a reference current, a first current generator controllable so as to inject a first variable current into the first input node, a second current generator controllable so as to inject a second variable current into the second input node, a first branch coupled to the first input node and comprising a first switch circuit, a first sense transistor and a first forcing transistor and a second branch coupled to the second input node and including a second switch circuit, a second sense transistor and a second forcing transistor.

公开(公告)号：US11049561B2

公开(公告)日：2021-06-29

申请号：US16903264

申请日：2020-06-16

Applicant: STMicroelectronics S.r.l.

Inventor： Fabio Enrico Carlo Disegni ,  Federico Goller ,  Cesare Torti ,  Marcella Carissimi ,  Emanuela Calvetti

IPC: G11C11/00 ,  G11C13/00

Abstract: A method for programming a phase-change-memory device of a differential type comprises, in a first programming mode, supplying, during a first time interval, a same first programming current, of a type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said first programming current; and, in a second programming mode, supplying, during a second time interval, a same second programming current, of the other type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said second programming current, thus completing, in just two time steps, writing of a logic word in the memory device.

公开(公告)号：US10319438B2

公开(公告)日：2019-06-11

申请号：US15797860

申请日：2017-10-30

Applicant: STMicroelectronics S.r.l.

Inventor： Emanuela Calvetti ,  Marcella Carissimi ,  Marco Pasotti

IPC: G11C7/00 ,  G11C13/00 ,  G11C16/26 ,  G11C11/16 ,  G11C7/06 ,  G11C16/24 ,  G11C16/28 ,  G11C16/34

Abstract: In accordance with an embodiment, a memory includes: a memory element, a sense amplifier circuit configured to sense a difference during a sense operation between a sense current passing through the memory element and a reference current, and a margin current branch coupled in parallel with the memory element and configured to selectively add a margin current to the sense current.